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user?s manual pd179322 pd179322a pd179324 pd179324a pd179326 pd179327 pd78f9328 pd179327 subseries 8-bit single-chip microcontrollers printed in japan document no. u16995ej2v0ud00 (2nd edition) date published april 2006 ns cp(k) 2004
2 user?s manual u16995ej2v0ud [memo]
user?s manual u16995ej2v0ud 3 1 2 3 4 voltage application waveform at input pin waveform distortion due to input noise or a reflected wave may cause malfunction. if the input of the cmos device stays in the area between v il (max) and v ih (min) due to noise, etc., the device may malfunction. take care to prevent chattering noise from entering the device when the input level is fixed, and also in the transition period when the input level passes through the area between v il (max) and v ih (min). handling of unused input pins unconnected cmos device inputs can be cause of malfunction. if an input pin is unconnected, it is possible that an internal input level may be generated due to noise, etc., causing malfunction. cmos devices behave differently than bipolar or nmos devices. input levels of cmos devices must be fixed high or low by using pull-up or pull-down circuitry. each unused pin should be connected to v dd or gnd via a resistor if there is a possibility that it will be an output pin. all handling related to unused pins must be judged separately for each device and according to related specifications governing the device. precaution against esd a strong electric field, when exposed to a mos device, can cause destruction of the gate oxide and ultimately degrade the device operation. steps must be taken to stop generation of static electricity as much as possible, and quickly dissipate it when it has occurred. environmental control must be adequate. when it is dry, a humidifier should be used. it is recommended to avoid using insulators that easily build up static electricity. semiconductor devices must be stored and transported in an anti-static container, static shielding bag or conductive material. all test and measurement tools including work benches and floors should be grounded. the operator should be grounded using a wrist strap. semiconductor devices must not be touched with bare hands. similar precautions need to be taken for pw boards with mounted semiconductor devices. status before initialization power-on does not necessarily define the initial status of a mos device. immediately after the power source is turned on, devices with reset functions have not yet been initialized. hence, power-on does not guarantee output pin levels, i/o settings or contents of registers. a device is not initialized until the reset signal is received. a reset operation must be executed immediately after power-on for devices with reset functions. power on/off sequence in the case of a device that uses different power supplies for the internal operation and external interface, as a rule, switch on the external power supply after switching on the internal power supply. when switching the power supply off, as a rule, switch off the external power supply and then the internal power supply. use of the reverse power on/off sequences may result in the application of an overvoltage to the internal elements of the device, causing malfunction and degradation of internal elements due to the passage of an abnormal current. the correct power on/off sequence must be judged separately for each device and according to related specifications governing the device. input of signal during power off state do not input signals or an i/o pull-up power supply while the device is not powered. the current injection that results from input of such a signal or i/o pull-up power supply may cause malfunction and the abnormal current that passes in the device at this time may cause degradation of internal elements. input of signals during the power off state must be judged separately for each device and according to related specifications governing the device. notes for cmos devices 5 6
4 user?s manual u16995ej2v0ud windows and windows nt are either re gistered trademarks or trademarks of microsoft corporation in the united states and/or other countries. pc/at is a trademark of internati onal business machines corporation. hp9000 series 700 and hp-ux are trad emarks of hewlett-packard company. sparcstation is a trademark of sparc international, inc. solaris and sunos are trademar ks of sun microsystems, inc. these commodities, technology or software, must be exported in accordance with the export administration regulations of the exporting country. diversion contrary to the law of that country is prohibited. the information in this document is current as of march, 2006. the information is subject to change without notice. for actual design-in, refer to the latest publications of nec electronics data sheets or data books, etc., for the most up-to-date specifications of nec electronics products. not all products and/or types are available in every country. please check with an nec electronics sales representative for availability and additional information. no part of this document may be copied or reproduced in any form or by any means without the prior written consent of nec electronics. nec electronics assumes no responsibility for any errors that may appear in this document. nec electronics does not assume any liability for infringement of patents, copyrights or other intellectual property rights of third parties by or arising from the use of nec electronics products listed in this document or any other liability arising from the use of such products. no license, express, implied or otherwise, is granted under any patents, copyrights or other intellectual property rights of nec electronics or others. descriptions of circuits, software and other related information in this document are provided for illustrative purposes in semiconductor product operation and application examples. the incorporation of these circuits, software and information in the design of a customer's equipment shall be done under the full responsibility of the customer. nec electronics assumes no responsibility for any losses incurred by customers or third parties arising from the use of these circuits, software and information. while nec electronics endeavors to enhance the quality, reliability and safety of nec electronics products, customers agree and acknowledge that the possibility of defects thereof cannot be eliminated entirely. to minimize risks of damage to property or injury (including death) to persons arising from defects in nec electronics products, customers must incorporat e sufficient safety measures in their design, such as redundancy, fire-containment and anti-failure features. nec electronics products are classified into the following three quality grades: "standard", "special" and "specific". the "specific" quality grade applies only to nec electronics products developed based on a customer- designated "quality assurance program" for a specific application. the recommended applications of an nec electronics product depend on its quality grade, as indicated below. customers must check the quality grade of each nec electronics product before using it in a particular application. the quality grade of nec electronics products is "standard" unless otherwise expressly specified in nec electronics data sheets or data books, etc. if customers wish to use nec electronics products in applications not intended by nec electronics, they must contact an nec electronics sales representative in advance to determine nec electronics' willingness to support a given application. (note) ? ? ? ? ? ? m8e 02. 11-1 (1) (2) "nec electronics" as used in this statement means nec electronics corporation and also includes its majority-owned subsidiaries. "nec electronics products" means any product developed or manufactured by or for nec electronics (as defined above). computers, office equipment, communications equipment, test and measurement equipment, audio and visual equipment, home electronic appliances, machine tools, personal electronic equipment and industrial robots. transportation equipment (automobiles, trains, ships, etc.), traffic control systems, anti-disaster systems, anti-crime systems, safety equipment and medical equipment (not specifically designed for life support). aircraft, aerospace equipment, submersible repeaters, nuclear reactor control systems, life support systems and medical equipment for life support, etc. "standard": "special": "specific":
user?s manual u16995ej2v0ud 5 [memo]
6 user?s manual u16995ej2v0ud introduction target readers this manual is intended for users who wish to understand the functions of the pd179327 subseries and to design and dev elop application systems and programs using these microcontrollers. target products: ? pd179327 subseries: pd179322, 179322a, 179324, 179324a, 179326, 179327 the pd78f9328 is used as the flas h memory version of the pd179327 subseries. purpose this manual is intended to give users an understanding of the f unctions described in the organization below. organization the pd179327 subseries user?s manual is divided into two parts: this manual and instructions (common to the 78k/0s series). pd179327 subseries user?s manual 78k/0s series user?s manual instructions ? pin functions ? internal block functions ? interrupt functions ? other on-chip peripheral functions ? electrical specifications ? cpu function ? instruction set ? explanation of each instruction how to use this manual it is assumed that the reader of this m anual has general knowledge in the fields of electrical engineering, logic circuits, and microcontrollers. ? to understand the functions in general: read this manual in the order of t he contents. the mark shows major revised points. the revised points can be easily searched by copying an ?? in the pdf file and specifying it in the ?find what:? field. ? how to interpret the register format: where the bit number is enclosed in angle brackets (<>), the bit name is reserved for the assembler and is defined as an sfr variable by the #pragma sfr directive for the c compiler. ? when you know a register name and want to confirm its details: read appendix b register index . ? to know the 78k/0s series in struction function in detail: read 78k/0s series instructions user?s manual (u11047e) . ? to know the pd179322, 179322a, 179324, 179324a, 179326, and 179327 electrical specification in details: read chapter 18 electrical specifications ( pd179322, 179322a, 179324, 179324a, 179326, and 179327) . ? to know the pd78f9328 electrical spec ification in details: read chapter 19 electrical specifications ( pd78f9328) .
user?s manual u16995ej2v0ud 7 conventions data significance: higher digits on the left and lower digits on the right active low representation: xxx (ove rscore over pin or signal name) note : footnote for item marked with note in the text caution : information requiring particular attention remark : supplementary information numerical representation: binary ... xxxx or xxxxb decimal ... xxxx hexadecimal ... xxxxh related documents the related documents indicated in this pub lication may include preliminary versions. however, preliminary versions are not marked as such. documents related to devices document name document no. pd179327 subseries user?s manual this manual 78k/0s series instructions user's manual u11047e documents related to developmen t software tools (user?s manuals) document name document no. operation u16656e language u14877e ra78k0s assembler package structured assembly language u11623e operation u16654e cc78k0s c compiler language u14872e operation u16768e sm78k series ver. 2.52 system simulator external part user open in terface specification u15802e id78k0s-ns ver. 2.52 integrated debugger operation u16584e pm plus ver.5.10 u16569e document related to development hardware tools (user?s manuals) document name document no. ie-78k0s-ns in-circuit emulator u13549e ie-78k0s-ns-a in-circuit emulator u15207e ie-789468-ns-em1 emulation board to be prepared caution the related documen ts listed above are subject to change without notice. be sure to use the latest version of each document for designing.
8 user?s manual u16995ej2v0ud documents related to flash memory writing document name document no. pg-fp4 flash memory progr ammer user's manual u15260e other related documents document name document no. semiconductor selection guide - products and packages - x13769x semiconductor device mount manual note quality grades on nec semiconductor devices c11531e nec semiconductor device reliability/quality control system c10983e guide to prevent damage for semiconductor devi ces by electrostatic discharge (esd) c11892e note see the ?semiconductor device mount manual? webs ite (http://www.necel.com/pkg/en/mount/index.html) caution the related documen ts listed above are subject to change without notice. be sure to use the latest version of each document for designing.
user?s manual u16995ej2v0ud 9 contents chapter 1 general ........................................................................................................... ............... 14 1.1 features.................................................................................................................. ....................... 14 1.2 applications .............................................................................................................. .................... 14 1.3 ordering information...................................................................................................... .............. 15 1.4 pin configuration (top view) .................................. ............................................................ ........ 16 1.5 179k series lineup ........................................................................................................ .............. 18 1.6 block diagram ............................................................................................................. ................. 19 1.7 overview of functions..................................................................................................... ............ 20 chapter 2 pin funct ions.................................................................................................... ........... 22 2.1 list of pin functions ..................................................................................................... ............... 22 2.2 description of pin functions .............................................................................................. ........ 24 2.2.1 p00 to p03 (por t 0) ..................................................................................................... ...................... 24 2.2.2 p10, p11 (por t 1) ....................................................................................................... ....................... 24 2.2.3 p20 to p22 (por t 2) ..................................................................................................... ...................... 24 2.2.4 p40 to p43 (por t 4) ..................................................................................................... ...................... 24 2.2.5 p60, p61 (por t 6) ....................................................................................................... ....................... 25 2.2.6 p80 to p85 (por t 8) ..................................................................................................... ...................... 25 2.2.7 s0 to s16, s23 .......................................................................................................... ........................ 25 2.2.8 com0 to com3 ............................................................................................................ .................... 25 2.2.9 v lc0 ............................................................................................................................... .................... 25 2.2.10 reset .................................................................................................................. .......................... 25 2.2.11 x1, x2 ................................................................................................................. ............................ 26 2.2.12 xt 1, xt2............................................................................................................... .......................... 26 2.2.13 v dd ............................................................................................................................... ................... 26 2.2.14 v ss ............................................................................................................................... ................... 26 2.2.15 v pp ( pd78f9328 only) ................................................................................................................ .. 26 2.2.16 ic0 (mask ro m versi on onl y) ............................................................................................ ............. 26 2.3 pin input/output circuits and recommended conn ection of unused pins .......................... 27 chapter 3 cpu architecture........................................ ......................................................... ..... 29 3.1 memory space .............................................................................................................. ................ 29 3.1.1 internal progr am memory space ........................................................................................... ............ 34 3.1.2 internal data memory (i nternal high-speed ram) spac e ................................................................... 3 5 3.1.3 special function register (s fr) area .................................................................................... ............. 35 3.1.4 data me mory addr essing .................................................................................................. ................ 36 3.2 processor registers ....................................................................................................... ............. 41 3.2.1 contro l regist ers....................................................................................................... ......................... 41 3.2.2 general-pur pose regi sters............................................................................................... .................. 44 3.2.3 special functi on register s (sfrs)....................................................................................... ............... 45 3.3 instruction address addressing................................. ........................................................... ..... 48 3.3.1 relati ve addre ssing ..................................................................................................... ...................... 48 3.3.2 immedi ate addre ssing .................................................................................................... ................... 49
10 user?s manual u16995ej2v0ud 3.3.3 table indi rect addr essing ............................................................................................... ................... 50 3.3.4 regist er addre ssing ..................................................................................................... ..................... 50 3.4 operand address a ddressing................................................................................................ .....51 3.4.1 direc t addre ssing ....................................................................................................... ....................... 51 3.4.2 short di rect addr essing ................................................................................................. .................... 52 3.4.3 special function r egister (sfr ) addre ssing .............................................................................. ......... 53 3.4.4 regist er addre ssing ..................................................................................................... ..................... 54 3.4.5 register i ndirect addr essing ............................................................................................ .................. 55 3.4.6 bas ed addre ssing ........................................................................................................ ...................... 56 3.4.7 sta ck addre ssing ........................................................................................................ ....................... 56 chapter 4 port functio ns ................................................................................................... ........57 4.1 port functions ............................................................................................................ ..................57 4.2 port configuration ........................................................................................................ ................58 4.2.1 po rt 0.................................................................................................................. ............................... 59 4.2.2 po rt 1.................................................................................................................. ............................... 60 4.2.3 po rt 2.................................................................................................................. ............................... 61 4.2.4 po rt 4.................................................................................................................. ............................... 64 4.2.5 po rt 6.................................................................................................................. ............................... 65 4.2.6 po rt 8.................................................................................................................. ............................... 67 4.3 registers controlling port function ....................................................................................... ...68 4.4 port function operation ................................................................................................... ...........72 4.4.1 writi ng to i/o port ..................................................................................................... ......................... 72 4.4.2 reading from i/o port................................................................................................... ..................... 72 4.4.3 arithmetic operation of i/o port ........................................................................................ ................. 72 chapter 5 clock generator .................................................................................................. ....73 5.1 clock generator functions ................................................................................................. ........73 5.2 clock generator configurat ion ............................................................................................. ......73 5.3 registers controlling clock generator...................... ............................................................... .75 5.4 system clock oscillators .................................................................................................. ..........77 5.4.1 main system clock osc illator ............................................................................................ .................. 77 5.4.2 subsystem clock osc illator .............................................................................................. .................. 78 5.4.3 example of incorre ct resonator connec tion ............................................................................... ........ 79 5.4.4 divider circ uit......................................................................................................... ............................ 80 5.4.5 when no subsyst em clock is used ......................................................................................... ........... 80 5.5 clock generator operat ion................................................................................................. .........81 5.6 changing setting of system clock and cpu clock.. ................................................................82 5.6.1 time required for switching between system clock and cpu cl ock................................................... 82 5.6.2 switching between syst em clock and cpu cl ock ............................................................................ .. 83
user?s manual u16995ej2v0ud 11 chapter 6 8-bit timers 30 and 40 ......................... ............................................................... ..... 84 6.1 8-bit timers 30 and 40 functions ............................... ........................................................... ..... 84 6.2 8-bit timers 30 and 40 configuration ....................... ............................................................... .. 85 6.3 registers controlling 8-bit timers 30 and 40 ........... ................................................................ 90 6.4 8-bit timers 30 and 40 operation .............................. ............................................................ ..... 95 6.4.1 operation as 8-bit time r count er........................................................................................ ................ 95 6.4.2 operation as 16-bit time r count er....................................................................................... ............. 102 6.4.3 operation as carrier generat or .......................................................................................... .............. 106 6.4.4 operation as pw m output (tim er 40 only) ................................................................................. ...... 110 6.5 notes on using 8-bit timers 30 and 40...................... ..............................................................1 12 chapter 7 watch timer ...................................................................................................... .........113 7.1 watch timer functions..................................................................................................... .........113 7.2 watch timer configuration ..................................... ............................................................ ......114 7.3 register controlling watch timer ............................. ............................................................. ..115 7.4 watch timer operation..................................................................................................... .........116 7.4.1 operation as watch timer ................................................................................................ ................ 116 7.4.2 operation as interval timer ............................................................................................. ................. 116 chapter 8 watchdog timer ................................................................................................... ....118 8.1 watchdog timer functions .................................................................................................. .....118 8.2 watchdog timer configuration.... .......................................................................................... ...119 8.3 registers controlling watchdog timer ....................... ............................................................120 8.4 watchdog timer operation .................................................................................................. .....122 8.4.1 operation as watchdog timer ............................................................................................. ............. 122 8.4.2 operation as interval timer ............................................................................................. ................. 123 chapter 9 serial interface 10 ( pd78f9328 only) ............................................................124 9.1 serial interface 10 functions ..................................... ........................................................ .......124 9.2 serial interface 10 configurat ion ......................................................................................... .....125 9.3 registers controlling serial interface 10.................. ............................................................... 127 9.4 serial interface 10 operation................................... .......................................................... ........129 9.4.1 operat ion stop mode ..................................................................................................... .................. 129 9.4.2 3-wire se rial i/o mode .................................................................................................. ................... 130 chapter 10 lcd controller/driver........................... ............................................................132 10.1 lcd controller/driver functions .............................. ............................................................ ..132 10.2 lcd controller/driver configuration....................... ............................................................... 132 10.3 registers controlling lcd controller/driver........... ..............................................................134 10.4 setting lcd controller/driver ............................................................................................ .....138 10.5 lcd display data memory.................................................................................................. .....139 10.6 common and segment signals ..............................................................................................1 40 10.7 display modes ............................................................................................................ ..............143 10.7.1 static di splay ex ample................................................................................................. .................. 143 10.7.2 four-time slot display example......................................................................................... ............. 146
12 user?s manual u16995ej2v0ud chapter 11 power-on-clear circuits ........................... ........................................................149 11.1 power-on-clear circuit functions ................................ ......................................................... .149 11.2 power-on-clear circuit confi guration....................................................................................1 49 11.3 register controlling power-on-clear circuit........... ..............................................................150 11.4 power-on-clear circuit operation ............................ ............................................................. .150 chapter 12 interrupt functions .................................... ........................................................1 51 12.1 interrupt function types ................................................................................................. ........151 12.2 interrupt sources and configur ation .....................................................................................1 51 12.3 registers controlling interrupt function...............................................................................15 4 12.4 interrupt servicing oper ation............................................................................................ ......158 12.4.1 non-maskable interrupt r equest acknowledgment operatio n......................................................... 158 12.4.2 maskable interrupt reques t acknowledgment operatio n ................................................................ 160 12.4.3 multiple in terrupt se rvicing........................................................................................... .................. 161 12.4.4 putting interr upt requests on hol d..................................................................................... ............. 163 chapter 13 standby function ................................................................................................ ..164 13.1 standby function and configurat ion .....................................................................................16 4 13.2 register controlling standby function .................................................................................165 13.3 standby function operation ............................................................................................... ....166 13.3.1 ha lt m ode .............................................................................................................. ..................... 166 13.3.2 st op m ode .............................................................................................................. .................... 169 chapter 14 reset function .................................................................................................. .....172 chapter 15 pd78f9328...................................................................................................................176 15.1 flash memory characteristi cs ............................................................................................. ...177 15.1.1 progra mming envir onment ................................................................................................ ............ 177 15.1.2 communi cation mode ..................................................................................................... .............. 178 15.1.3 on-board pin proc essing ................................................................................................ ............... 180 15.1.4 connection on flash memory writ ing adapt er ............................................................................. ... 183 chapter 16 mask options .................................................................................................... .......184 chapter 17 instruction set ................................................................................................. .....185 17.1 operation................................................................................................................ ...................185 17.1.1 operand identifiers and descripti on met hods ............................................................................ .... 185 17.1.2 description of ?operation? column...................................................................................... ........... 186 17.1.3 description of ?flag? column........................................................................................... ............... 186 17.2 operation list ........................................................................................................... ................187 17.3 instructions listed by a ddressing type................................................................................192
user?s manual u16995ej2v0ud 13 chapter 18 electrical specifications ( pd179322, 179322a, 179324, 179324a, 179326, and 179327) ....... ............................................................................................................. ........................195 chapter 19 electrical specifications ( pd78f9328)........................................................205 chapter 20 package drawing ...................................... ........................................................... .217 chapter 21 recommended soldering conditions .. ........................................................218 appendix a development tools ..............................................................................................2 20 a.1 software package .......................................................................................................... ............222 a.2 language processing software ................................... ........................................................... .222 a.3 control software .......................................................................................................... ..............223 a.4 flash memory writing tools................................................................................................ .....223 a.5 debugging tools (hardware)........................................ ........................................................ ....224 a.6 debugging tools (software)....................................... ......................................................... .....225 a.7 cautions when designing target system................... ..............................................................226 appendix b register index .................................................................................................. .......227 b.1 register index (alphabetic order of register na me) ............................................................227 b.2 register index (alphabetic order of register sy mbol) .........................................................229 appendix c revision history ................................................................................................. .....231 c.1 major revisions in this edition ........................................................................................... ....231 c.2 revision history of preceding editions .................... ..............................................................23 1
14 user?s manual u16995ej2v0ud chapter 1 general 1.1 features rom and ram capacities item data memory part number program memory (rom) internal high-speed ram lcd display ram pd179322 pd179322a 4 kb pd179324 pd179324a 8 kb 256 bytes pd179326 16 kb pd179327 mask rom 24 kb pd78f9328 flash memory 32 kb 512 bytes 24 4 bits minimum instruction execution ti me can be changed from high-speed (0.4 s: @ 5.0 mhz operation with main system clock) to ultra-low-speed (122 s: @ 32.768 khz operation with subsystem clock) i/o ports: 21 serial interface (3-wire serial i/o mode): 1 channel timer: 4 channels 8-bit timer: 2 channels watch timer: 1 channel watchdog timer: 1 channel lcd controller/driver segment signals: 24, common signals: 4 vectored interrupt sources mask rom versions: 8 flash memory version: 9 on-chip power-on clear circuit (mask option for mask rom versions) power supply voltage mask rom versions: v dd = 1.8 to 3.6 v note flash memory version: v dd = 1.8 to 5.5 v note operating ambient temperature: t a = ?40 to +85 c note for mask rom version when the use of the poc circui t is selected or for flash memory versions, the minimum value of the operation power suppl y voltage is the poc detection voltage (1.9 0.1 v). 1.2 applications remote controllers for air conditioners, av equipments, and water flow (in toilets, baths, etc.), etc.
chapter 1 general user?s manual u16995ej2v0ud 15 1.3 ordering information part number package internal rom pd179322gb- -8et 52-pin plastic lqfp (10 10) mask rom pd179322agb- -8et 52-pin plastic lqfp (10 10) mask rom pd179324gb- -8et 52-pin plastic lqfp (10 10) mask rom pd179324agb- -8et 52-pin plastic lqfp (10 10) mask rom pd179326gb- -8et 52-pin plastic lqfp (10 10) mask rom pd179327gb- -8et 52-pin plastic lqfp (10 10) mask rom pd179322gb- -8et-a 52-pin plastic lqfp (10 10) mask rom pd179322agb- -8et-a 52-pin plastic lqfp (10 10) mask rom pd179324gb- -8et-a 52-pin plastic lqfp (10 10) mask rom pd179324agb- -8et-a 52-pin plastic lqfp (10 10) mask rom pd179326gb- -8et-a 52-pin plastic lqfp (10 10) mask rom pd179327gb- -8et-a 52-pin plastic lqfp (10 10) mask rom pd78f9328gb-8et 52-pin plastic lqfp (10 10) flash memory pd78f9328gb-8et-a 52-pin plastic lqfp (10 10) flash memory remarks 1. indicates rom code suffix. 2. products that have the part numbers su ffixed by "-a" are lead-free products.
chapter 1 general 16 user?s manual u16995ej2v0ud 1.4 pin configuration (top view) 52-pin plastic lqfp (10 10) reset p60/to40 p43/kr03 p42/kr02 p41/kr01 p40/kr00 p03 p02 p01 p00 int/p61 x1 x2 v dd v ss xt2 xt1 ic0 (v pp ) p20/sck10 note p21/so10 note p22/si10 note v lc0 52 51 50 49 48 47 46 45 44 43 42 14 15 16 17 18 19 20 21 22 23 24 1 2 3 4 5 6 7 8 9 10 11 39 38 37 36 35 34 33 32 31 30 29 p11 p10 p81/s21 p82/s20 p83/s19 p84/s18 p85/s17 s16 s15 s14 s13 s12 s11 s10 s9 com0 com1 com2 com3 s0 s1 s2 s3 s4 s5 s6 s7 s8 s23 p80/s22 12 13 28 27 41 40 25 26 note sck10, so10, and si10 are provided in the pd78f9328 only. caution connect the ic0 (internally connected) pin directly to v ss . remark the parenthesized values apply to the pd78f9328.
chapter 1 general user?s manual u16995ej2v0ud 17 com0 to com3: common output s0 to s23: segment output ic0: internally connected sck 10: serial clock input/output int: interrupt from peripheral s si10: serial data input kr00 to kr03: key return so10: serial data output p00 to p03: port 0 to40: timer output p10, p11: port 1 v dd : power supply p20 to p22: port 2 v lc0 : power supply for lcd p40 to p43: port 4 v pp : programming power supply p60, p61: port 6 v ss : ground p80 to p85: port 8 x1, x2: crystal (main system clock) reset: reset xt1, xt2: crystal (subsystem clock)
chapter 1 general 18 user?s manual u16995ej2v0ud 1.5 179k series lineup the products in the 179k series are listed below. the names enclosed in box es are subseries names. 52-pin on-chip the resistance division type lcd (24 4) pd179327 for pre-set remote controller 179k series on-chip the low-voltage detector, the data retention voltage detector, and key return circuit 30-pin pd179088 for lcd remote controller the major differences between subseries are shown below. timer v dd function subseries rom capacity (bytes) 8-bit 16-bit watch wdt i/o min.value remarks for pre-set remote controller pd179088 16 k-32 k 3 ch 1 ch 1 ch 1 ch 24 1.8 v ? for lcd remote controller pd179327 4 k to 24 k 2 ch ? 1 ch 1 ch 21 1.8 v ?
chapter 1 general user?s manual u16995ej2v0ud 19 1.6 block diagram v dd v ss ic0 (v pp ) 78k/0s cpu core rom (flash memory) 8-bit timer 30 p00 to p03 port 0 p10, p11 port 1 p20 to p22 port 2 p40 to p43 port 4 p60, p61 port 6 watchdog timer s0 to s23 com0 to com3 ram ram space for lcd data 8-bit timer 40 cascaded 16-bit timer serial interface 10 note1 sck10 note1 /p20 si10 note1 /p22 so10 note1 /p21 v lc0 lcd controller/driver system control reset x1 x2 xt1 xt2 interrupt control kr00/p40 to kr03/p43 int/p61 p80 to p85 port 8 watch timer to40/p60 power-on clear note2 notes 1. the serial interface 10 is provided in the pd78f9328 only. 2. only when use of the poc circuit is selected by a mask option in the case of mask rom versions ( pd179322, 179322a, 179324, 179324a, 179326, and 179327). remarks 1. the internal rom and ram capac ities vary depending on the product. 2. the parenthesized values apply to the pd78f9328.
chapter 1 general 20 user?s manual u16995ej2v0ud 1.7 overview of functions pd179327 subseries pd789327 subseries part number item pd179322 pd179322a pd179324 pd179324a pd179326 pd179327 pd78f9328 mask rom flash memory rom 4 kb 8 kb 16 kb 24 kb 32 kb high-speed ram 256 bytes 512 bytes internal memory lcd display ram 24 4 bits main system clock (oscillation frequency) cerami c/crystal oscillation (1.0 to 5.0 mhz) subsystem clock (oscillation frequency) crystal oscillation (32.768 khz) 0.4 s/1.6 s (@ 5.0 mhz operation with main system clock) minimum instruction execution time 122 s (@ 32.768 khz operation with subsystem clock) general-purpose registers 8 bits 8 registers instruction set 16-bit operations bit manipulations (such as set, reset, and test) i/o ports cmos i/o: 21 note 1 timers 8-bit timer: 2 channels watch timer: 1 channel watchdog timer: 1 channel timer outputs 1 serial interface ? 3-wire serial i/o mode: 1 channel lcd controller/driver segment signal outputs: 24 note 1 common signal outputs: 4 mode: static mode and 1/3 bias mode maskable internal: 5 external: 2 internal: 6 external: 2 vectored interrupt sources non-maskable internal: 1 reset reset by reset input internal reset by watchdog timer reset by power-on-clear circuit note 2 power supply voltage v dd = 1.8 to 3.6 v note 3 v dd = 1.8 to 5.5 v note 3 operating ambient temperature t a = ? 40 to + 85c package 52-pin plastic lqfp (10 10) notes 1. six among these pins are used to se lect either port function or lcd segment output via the port function register. 2. for mask rom versions ( pd179322, 179322a, 179324, 179324a, 179326, 179327) , this is available only when the use of poc circui t is selected by mask option. 3. for mask rom versions when the use of the poc circui t is selected or for flash memory versions, the minimum value of the operation power suppl y voltage is the poc detection voltage (1.9 0.1 v).
chapter 1 general user?s manual u16995ej2v0ud 21 an outline of the timer is shown below. 8-bit timer 30 8-bit timer 40 watch timer watchdog timer interval timer 1 channel 1 channel 1 channel note 1 1 channel note 2 operation mode external event counter ? ? ? ? timer outputs ? 1 output ? ? square-wave outputs ? 1 output ? ? capture ? ? ? ? function interrupt sources 1 1 2 2 notes 1. the watch timer can perform both watch timer and interval timer functions at the same time. 2. the watchdog timer has the watchdog timer and interv al timer functions. however, use the watchdog timer by selecting either the watchdog time r function or interval timer function.
22 user?s manual u16995ej2v0ud chapter 2 pin functions 2.1 list of pin functions (1) port pins pin name i/o function after reset alternate function p00 to p03 input/ output port 0. this is a 4-bit i/o port. input/output can be specified in 1-bit units. when used as an input port, on-chip pull-up resistors can be specified in port units using pu ll-up resistor option register 0 (pu0). input ? p10, p11 input/ output port 1. this is a 2-bit i/o port. input/output can be specified in 1-bit units. when used as an input port, on-chip pull-up resistors can be specified in port units using pu ll-up resistor option register 0 (pu0). input ? p20 sck10 note p21 so10 note p22 input/ output port 2. this is a 3-bit i/o port. input/output can be specified in 1-bit units. on-chip pull-up resistors can be s pecified in 1-bit units using pull-up resistor option register 2 (pub2). input si10 note p40 to p43 input/ output port 4. this is a 4-bit i/o port. input/output can be specified in 1-bit units. when used as an input port, on-chip pull-up resistors can be specified in port units using pu ll-up resistor option register 0 (pu0), or key return mode register 00 (krm00). input kr00 to kr03 p60 to40 p61 input/ output port 6. this is a 2-bit i/o port. input/output can be specified in 1-bit units. input int p80 to p85 input/ output port 8. this is a 6-bit i/o port. input/output can be specified in 1-bit units. input s22 to s17 note sck10, so10, and si10 are provided in pd78f9328 only.
chapter 2 pin functions user?s manual u16995ej2v0ud 23 (2) non-port pins pin name i/o function after reset alternate function int input external interrupt input for which the valid edge (rising edge, falling edge, or both rising and falling edges) can be specified. input p61 kr00 to kr03 input key return signal detection input p40 to p43 to40 output 8-bit timer 40 output input p60 sck10 note input/ output serial clock input/output of serial interface 10 input p20 si10 note input serial data input of serial interface 10 input p22 so10 note output serial data output of serial interface 10 input p21 s0 to s16 low-level output ? s17 to s22 input p85 to p80 s23 output lcd controller/driver segment signal outputs low-level output ? com0 to com3 output lcd controller/ driver common signal outputs low-level output ? v lc0 ? lcd drive voltage ? ? x1 input ? ? x2 ? connecting crystal/ceramic resonator for main system clock oscillation ? ? xt1 input ? ? xt2 ? connecting crystal resonator fo r subsystem clock oscillation ? ? reset input system reset input input ? v dd ? positive power supply ? ? v ss ? ground potential ? ? ic0 ? internally connected. connect directly to v ss . ? ? v pp ? sets flash memory programming mode. applies high voltage when a program is written or verified. ? ? note sck10, so10, and si10 are provided in pd78f9328 only.
chapter 2 pin functions 24 user?s manual u16995ej2v0ud 2.2 description of pin functions 2.2.1 p00 to p03 (port 0) these pins constitute a 4-bit i/o port and can be set in t he input or output port mode in 1-bit units by port mode register 0 (pm0). when used as an input port, use of an on-chip pull-up resistor can be specified by pull-up resistor option register 0 (pu0) in port units. 2.2.2 p10, p11 (port 1) these pins constitute a 2-bit i/o port and can be set in t he input or output port mode in 1-bit units by port mode register 1 (pm1). when used as an input port, use of an on-chip pull-up resistor can be specified by pull-up resistor option register 0 (pu0) in port units. 2.2.3 p20 to p22 (port 2) these pins constitute a 3-bit i/o port. in addition, t hese pins enable serial interface data i/o and clock i/o in pd78f9328 only. port 2 can be specified in the follo wing operation modes in 1-bit units. (1) port mode in this mode, p20 to p22 function as a 3-bit i/o port. port 2 can be set in the i nput or output port mode in 1- bit units by port mode register 2 (pm2 ). use of an on-chip pull-up resistor can be specified by pull-up resistor option register b2 (pub2) in 1-bit units. (2) control mode in this mode, p20 to p22 function as the serial interface data i/o and clock i/o. (a) si10 note , so10 note these are the serial data i/o pins of the serial interface. (b) sck10 note this is the serial clock i/o pin of the serial interface. note sck10, so10, and si10 are provided in pd78f9328 only. caution when using p20 to p22 as serial interf ace pins, the i/o mode and output latch must be set according to the functions to be used. for the details of the setting, refer to table 9-2 settings of serial interface 10 operating mode. 2.2.4 p40 to p43 (port 4) these pins constitute a 4-bit i/o port. in addition, they also function as key return signal detection. port 4 can be specified in the fo llowing operation mode in 1-bit units. (1) port mode in this mode, port 4 functions as a 4-bit i/o port. port 4 can be set in the input or output port mode in 1-bit units by port mode register 4 (pm4). when used as an input port, use of an on-ch ip pull-up resistor can be specified by pull-up resistor option register 0 (pu0) or key return mode register 00 (krm00) in port units.
chapter 2 pin functions user?s manual u16995ej2v0ud 25 (2) control mode in this mode, the pins function as ke y return signal detection (kr00 to kr03). 2.2.5 p60, p61 (port 6) these pins constitute a 2-bit i/o port. in addition, they al so function as timer output and external interrupt input. port 6 can be specified in the fo llowing operation mode in 1-bit units. (1) port mode in this mode, port 6 functions as a 2-bit i/o port. port 6 can be set in the input or output port mode in 1-bit units by port mode register 6 (pm6). (2) control mode in this mode, the pins function as ti mer output and external interrupt input. (a) to40 this is the timer output pin to timer 40. (b) int this is the external interrupt input pin for wh ich valid edges (rising edge, falling edge, or both rising and falling edges) can be specified. 2.2.6 p80 to p85 (port 8) these pins constitute a 6-bit i/o port. in addition, they al so function as lcd controller/ driver segment signal output. port 8 can be specified in the follo wing operation mode in 1-bit units by port function register 8 (pf8). (1) port mode in this mode, port 8 functions as a 6-bit i/o port. port 8 can be set in the input or output port mode in 1-bit units by port mode register 8 (pm8). (2) control mode in this mode, the pins function as lcd contro ller/driver segment signal output (s17 to s22). 2.2.7 s0 to s16, s23 these pins are segment signal output pins for the lcd controller/driver. 2.2.8 com0 to com3 these pins are common signal output pi ns for the lcd controller/driver. 2.2.9 v lc0 this pin is the power supply voltage pin to drive the lcd. 2.2.10 reset this pin inputs an active-low system reset signal.
chapter 2 pin functions 26 user?s manual u16995ej2v0ud 2.2.11 x1, x2 these pins are used to connect a crystal/ceramic resonator for main system clock oscillation. to supply an external clock, input the clo ck to x1 and input the inverted signal to x2. 2.2.12 xt1, xt2 these pins are used to connect a crystal re sonator for subsystem clock oscillation. to supply an external clock, input the clock to xt1 and input the inverted signal to xt2. 2.2.13 v dd this is the positive power supply pin. 2.2.14 v ss this is the ground pin. 2.2.15 v pp ( pd78f9328 only) a high voltage should be applied to this pin when the flash memory programming mode is set and when the program is written or verified. perform either of the following. ? independently connect a 10 k ? pull-down resistor to v pp . ? use the jumper on the board to connect v pp to the dedicated flash programmer or v ss , in programming mode or normal operation mode, respectively. if the wiring between the v pp and v ss pins is long or external noise is superimposed on the v pp pin, the userprogram may not run correctly. 2.2.16 ic0 (mask rom version only) the ic0 (internally connected) pin is used to set the pd179322, 179322a, 179324, 179324a, 179326, and 179327 in the test mode before shipment. in the normal operation mode, directly c onnect this pin to the v ss pin with as short a wiring length as possible. if a potential difference is gener ated between the ic0 pin and v ss pin due to a long wiring length, or an external noise superimposed on the ic0 pin, the user program may not run correctly. ? directly connect the ic0 pin to the v ss pin. v ss ic0 keep short
chapter 2 pin functions user?s manual u16995ej2v0ud 27 2.3 pin input/output circuits and r ecommended connection of unused pins the input/output circuit type of eac h pin and recommended connection of unused pi ns are shown in table 2-1. for the input/output circuit configurat ion of each type, see figure 2-1. table 2-1. types of pin i/o circuits a nd recommended connection of unused pins pin name i/o circuit type i/o re commended connection of unused pins p00 to p03 p10, p11 5-a p20/sck10 note1 p21/so10 note1 p22/si10 note1 p40/kr00 to p43/kr03 8-a p60/to40 5 input: independently connect to v dd or v ss via a resistor. output: leave open. p61/int 8 input: independently connect to v ss via a resistor. output: leave open. p80/s22 to p85/s17 17-n i/o input: independently connect to v dd or v ss via a resistor. output: leave open. s0 to s16, s23 17-d com0 to com3 18-b output leave open. v lc0 ? connect to v dd note2 . xt1 input connect to v ss . xt2 ? ? leave open. reset 2 input ? ic0 (mask rom version) connect directly to v ss . v pp ( pd78f9328) ? ? independently connect v pp to a 10 k ? pull-down resistor or directly connect to v ss . notes 1. sck10, so10, and si10 are provided in pd78f9328 only. 2. the current flows from v lc0 to v ss via the lcd division resistors. figure 2-1. i/o circuit type (1/2) type 2 type 5 schmitt-triggered input with hysteresis characteristics. in p-ch in/out data output disable input enable v dd n-ch v ss
chapter 2 pin functions 28 user?s manual u16995ej2v0ud figure 2-1. i/o circuit type (2/2) type 5-a type 8 pull-up enable v dd p-ch p-ch in/out data output disable input enable v dd n-ch v ss data v dd p-ch output disable in/out n-ch v ss type 8-a type 17-d pull-up enable v dd p-ch data v dd p-ch output disable in/out n-ch v ss p-ch n-ch p-ch n-ch n-ch n-ch data out v lc0 v lc1 seg v lc2 p-ch p-ch v ss type 17-n type 18-b p-ch n-ch p-ch n-ch n-ch n-ch data v lc0 v lc1 seg v lc2 p-ch p-ch v ss p-ch in/out data output disable input enable v lc0 v dd n-ch v ss p-ch n-ch p-ch n-ch p-ch n-ch p-ch n-ch data p-ch n-ch v lc1 v lc0 v lc2 out com v ss remark v lc1 : v lc0 2/3, v lc2 : v lc0 /3
user?s manual u16995ej2v0ud 29 chapter 3 cpu architecture 3.1 memory space the pd179327 subseries can access 64 kb of memory space. figures 3-1 through 3-5 show the memory maps. figure 3-1. memory map ( pd179322 and 179322a) special function registers 256 8 bits internal high-speed ram 256 8 bits lcd display ram 24 4 bits reserved reserved internal rom 4096 8 bits ffffh ff00h feffh fe00h fdffh fa00h f9ffh 0000h program memory space data memory space 0fffh 0000h program area 0080h 007fh program area 0040h 003fh callt table area 0014h 0013h vector table area fa18h fa17h 1000h 0fffh
chapter 3 cpu architecture 30 user?s manual u16995ej2v0ud figure 3-2. memory map ( pd179324 and 179324a) special function registers 256 8 bits internal high-speed ram 256 8 bits internal rom 8192 8 bits ffffh ff00h feffh 0000h program memory space data memory space 1fffh 0000h program area 0080h 007fh program area 0040h 003fh callt table area 0014h 0013h vector table area lcd display ram 24 4 bits reserved reserved fe00h fdffh fa00h f9ffh fa18h fa17h 2000h 1fffh
chapter 3 cpu architecture user?s manual u16995ej2v0ud 31 figure 3-3. memory map ( pd179326) special function registers 256 8 bits internal high-speed ram 512 8 bits internal rom 16384 8 bits ffffh ff00h feffh 0000h program memory space data memory space 3fffh 0000h program area 0080h 007fh program area 0040h 003fh callt table area 0014h 0013h vector table area lcd display ram 24 4 bits reserved reserved fd00h fcffh fa00h f9ffh fa18h fa17h 4000h 3fffh
chapter 3 cpu architecture 32 user?s manual u16995ej2v0ud figure 3-4. memory map ( pd179327) special function registers 256 8 bits internal high-speed ram 512 8 bits internal rom 24576 8 bits ffffh ff00h feffh 0000h program memory space data memory space 5fffh 0000h program area 0080h 007fh program area 0040h 003fh callt table area 0014h 0013h vector table area lcd display ram 24 4 bits reserved reserved fd00h fcffh fa00h f9ffh fa18h fa17h 6000h 5fffh
chapter 3 cpu architecture user?s manual u16995ej2v0ud 33 figure 3-5. memory map ( pd78f9328) special function registers 256 8 bits internal high-speed ram 512 8 bits flash memory 32768 8 bits ffffh ff00h feffh 0000h program memory space data memory space 7fffh 0000h program area 0080h 007fh program area 0040h 003fh callt table area 0014h 0013h vector table area lcd display ram 24 4 bits reserved reserved fd00h fcffh fa00h f9ffh fa18h fa17h 8000h 7fffh
chapter 3 cpu architecture 34 user?s manual u16995ej2v0ud 3.1.1 internal program memory space the internal program memory space stores programs and table data. this space is usually addressed by the program counter (pc). the pd179327 subseries provide internal rom (or flash memory) with the following capacity for each product. table 3-1. internal rom capacity part number internal rom structure capacity pd179322 and 179322a 4096 8 bits pd179324 and 179324a 8192 8 bits pd179326 16384 8 bits pd179327 mask rom 24576 8 bits pd78f9328 flash memory 32768 8 bits the following areas are allocated to t he internal program memory space. (1) vector table area the 20-byte area of addresses 0000h to 0013h is reserved as a vector table area. this area stores program start addresses to be used when branching by the reset input or an interrupt request generation. of a 16- bit program address, the lower 8 bi ts are stored in an even address, and the higher 8 bits are stored in an odd address. table 3-2. vector table vector table address interrupt request vector table address interrupt request 0000h reset input 000ch inttm30 0004h intwdt 000eh inttm40 0006h intp0 0010h intkr00 0008h note intcsi10 note 0012h intwti 000ah intwt note the pd78f9328 only (2) callt instruction table area the subroutine entry address of a 1-byte call instruction (callt) can be stored in the 64-byte area of addresses 0040h to 007fh.
chapter 3 cpu architecture user?s manual u16995ej2v0ud 35 3.1.2 internal data memory (internal high-speed ram) space the pd179327 subseries products inco rporate the following ram. (1) internal high-speed ram internal high-speed ram is incorporated in the area between fe00h and feffh in the pd179322, 179322a, 179324 and 179324a, and in the area between fd00h and feffh in the pd179326, 179327, and 78f9328. instructions cannot be written to this on-chip high-speed ram as a program area for execution. the internal high-speed ram is also used as a stack. (2) lcd display ram lcd display ram is allocated in the area between fa00h and fa17h. the lcd display ram can also be used as ordinary ram. 3.1.3 special function register (sfr) area special function registers (sfrs) of on-chip peripheral hardware are a llocated in the area between ff00h and ffffh (see table 3-3 ).
chapter 3 cpu architecture 36 user?s manual u16995ej2v0ud 3.1.4 data memory addressing the pd179327 subseries are provided with a variety of addressing modes to make memory manipulation as efficient as possible. at the addresses corresponding to data memory area especially, s pecific addressing modes that correspond to the particular function an area, such as the special function register s are available. figures 3-6 through 3-10 show the data memory addressing modes. figure 3-6. data memory addressing ( pd179322 and 179322a) special function registers (sfrs) 256 8 bits internal high-speed ram 256 8 bits internal rom 4096 8 bits ffffh 0000h direct addressing register indirect addressing based addressing ff00h feffh ff20h ff1fh fe20h fe1fh sfr addressing short direct addressing lcd display ram 24 4 bits reserved reserved fe00h fdffh fa00h f9ffh 1000h 0fffh fa18h fa17h
chapter 3 cpu architecture user?s manual u16995ej2v0ud 37 figure 3-7. data memory addressing ( pd179324 and 179324a) special function registers (sfrs) 256 8 bits internal high-speed ram 256 8 bits internal rom 8192 8 bits ffffh 0000h direct addressing register indirect addressing based addressing ff00h feffh ff20h ff1fh fe20h fe1fh sfr addressing short direct addressing lcd display ram 24 4 bits reserved reserved fe00h fdffh fa00h f9ffh 2000h 1fffh fa18h fa17h
chapter 3 cpu architecture 38 user?s manual u16995ej2v0ud figure 3-8. data memory addressing ( pd179326) special function registers (sfrs) 256 8 bits internal high-speed ram 512 8 bits internal rom 16384 8 bits ffffh 0000h direct addressing register indirect addressing based addressing ff00h feffh ff20h ff1fh fe20h fe1fh sfr addressing short direct addressing lcd display ram 24 4 bits reserved reserved fd00h fcffh fa00h f9ffh 4000h 3fffh fa18h fa17h
chapter 3 cpu architecture user?s manual u16995ej2v0ud 39 figure 3-9. data memory addressing ( pd179327) special function registers (sfrs) 256 8 bits internal high-speed ram 512 8 bits internal rom 24576 8 bits ffffh 0000h direct addressing register indirect addressing based addressing ff00h feffh ff20h ff1fh fe20h fe1fh sfr addressing short direct addressing lcd display ram 24 4 bits reserved reserved fd00h fcffh fa00h f9ffh 6000h 5fffh fa18h fa17h
chapter 3 cpu architecture 40 user?s manual u16995ej2v0ud figure 3-10. data memory addressing ( pd78f9328) special function registers (sfrs) 256 8 bits internal high-speed ram 512 8 bits flash memory 32768 8 bits ffffh 0000h direct addressing register indirect addressing based addressing ff00h feffh ff20h ff1fh fe20h fe1fh sfr addressing short direct addressing lcd display ram 24 4 bits reserved reserved fd00h fcffh fa00h f9ffh 8000h 7fffh fa18h fa17h
chapter 3 cpu architecture user?s manual u16995ej2v0ud 41 3.2 processor registers the pd179327 subseries provide the followi ng on-chip processor registers. 3.2.1 control registers the control registers contai n special functions to cont rol the program sequence status es and stack memory. the program counter, program status word, and stack pointer are c ontrol registers. (1) program counter (pc) the program counter is a 16-bit r egister that holds the address info rmation of the next program to be executed. in normal operation, the pc is automat ically incremented according to the number of bytes of the instruction to be fetched. when a branch instruction is execut ed, immediate data or r egister contents are set. reset input sets the reset vector table values at addresses 0000h and 0001h to the program counter. figure 3-11. program counter configuration 0 15 pc14 pc15 pc pc13 pc12 pc11 pc10 pc9 pc8 pc7 pc6 pc5 pc4 pc3 pc2 pc1 pc0 (2) program status word (psw) the program status word is an 8-bit register consisting of various flags to be set/reset by instruction execution. the program status word contents are automatica lly stacked upon interrupt request generation or push psw instruction execution and ar e automatically restored upon exec ution of the reti and pop psw instructions. reset input sets psw to 02h. figure 3-12. program status word configuration 70 ie z 0 ac 0 0 1 cy psw
chapter 3 cpu architecture 42 user?s manual u16995ej2v0ud (a) interrupt enable flag (ie) this flag controls interrupt request a cknowledgement operati ons of the cpu. when 0, ie is set to the interrupt disable stat us (di), and interrupt reques ts other than non-maskable interrupt are all disabled. when 1, ie is set to the interrupt enable status (ei). interrupt request acknowledgement enable is controlled with an interrupt mask flag for various interrupt sources. ie is reset (0) upon di instruction execution or interrupt acknowledgment and is set (1) upon ei instruction execution. (b) zero flag (z) when the operation result is zero, this flag is se t (1). it is reset (0) in all other cases. (c) auxiliary carry flag (ac) if the operation result has a carry from bit 3 or a borrow at bit 3, this flag is set (1). it is reset (0) in all other cases. (d) carry flag (cy) this flag stores overflow and underfl ow upon add/subtract instruction exec ution. it stores the shift-out value upon rotate instruction execution and functions as a bit accumulator during bit manipulation instruction execution.
chapter 3 cpu architecture user?s manual u16995ej2v0ud 43 (3) stack pointer (sp) this is a 16-bit register to hold t he start address of the memory stack area. only the internal high-speed ram area can be set as the stack area. figure 3-13. stack pointer configuration 0 15 sp14 sp15 sp sp13 sp12 sp11 sp10 sp9 sp8 sp7 sp6 sp5 sp4 sp3 sp2 sp1 sp0 the sp is decremented ahead of write (save) to the stack memory and is incremented after read (restore) from the stack memory. each stack operation saves/restores dat a as shown in figures 3-14 and 3-15. caution since reset input makes the sp contents unde fined, be sure to initialize the sp before instruction execution. figure 3-14. data to be saved to stack memory interrupt psw pc15 to pc8 pc15 to pc8 pc7 to pc0 lower register pairs sp sp _ 2 sp _ 2 call, callt instructions push rp instruction sp _ 1 sp sp sp _ 2 sp _ 2 sp _ 1 sp pc7 to pc0 sp _ 3 sp _ 2 sp _ 1 sp sp sp _ 3 higher register pairs figure 3-15. data to be restored from stack memory reti instruction psw pc15 to pc8 pc15 to pc8 pc7 to pc0 lower register pairs ret instruction pop rp instruction sp pc7 to pc0 higher register pairs sp + 1 sp sp + 2 sp sp + 1 sp sp + 2 sp sp + 1 sp + 2 sp sp + 3
chapter 3 cpu architecture 44 user?s manual u16995ej2v0ud 3.2.2 general-purpose registers the general-purpose register s consist of eight 8-bit registers (x, a, c, b, e, d, l, and h). each register can be used as an 8-bit r egister, or two 8-bit registers in pairs can be used as a 16-bit register (ax, bc, de, and hl). general-purpose registers can be described in terms of function names (x, a, c, b, e, d, l, h, ax, bc, de, or hl) or absolute names (r0 to r7 and rp0 to rp3). figure 3-16. general-purpo se register configuration (a) absolute names r0 15 0 7 0 16-bit processing 8-bit processing rp3 rp2 rp1 rp0 r1 r2 r3 r4 r5 r6 r7 (b) function names x 15 0 7 0 16-bit processing 8-bit processing hl de bc ax a c b e d l h
chapter 3 cpu architecture user?s manual u16995ej2v0ud 45 3.2.3 special function registers (sfrs) unlike a general-purpose register, each special function register has a special function. the special function registers are allocat ed in the 256-byte area of ff00h to ffffh. special function registers can be m anipulated, like general-purpos e registers, by operat ion, transfer, and bit manipulation instructions. the manipul atable bit units (1, 8, and 16) differ depending on the special function register type. the manipulatable bits can be specified as follows. 1-bit manipulation describes a symbol reserved by the assembler for the 1-bit manipulation instructi on operand (sfr.bit). this manipulation can also be specified with an address. 8-bit manipulation describes a symbol reserved by the assembler for t he 8-bit manipulation instru ction operand (sfr). this manipulation can also be specified with an address. 16-bit manipulation describes a symbol reserved by the assembler fo r the 16-bit manipulation instruction operand. when addressing an address, describe an even address. table 3-3 lists the special function r egisters. the meanings of the symbol s in this table are as follows: symbol indicates the addresses of the impl emented special function r egisters. the symbols shown in this column are reserved for the assembler and are defined as an sfr vari able by the #pragma sfr dire ctive for the c compiler. therefore, these symbols c an be used as instruction operands if an a ssembler or integrated debugger is used. r/w indicates whether the special function r egister in question can be read or written. r/w: read/write r: read only w: write only bit unit for manipulation indicates the bit units (1, 8, 16) in which the s pecial function register in question can be manipulated. after reset indicates the status of t he special function register w hen the reset signal is input.
chapter 3 cpu architecture 46 user?s manual u16995ej2v0ud table 3-3. special function registers (1/2) bit unit for manipulation address special function regist er (sfr) name symbol r/w 1 bit 8 bits 16 bits after reset ff00h port 0 p0 ? ff01h port 1 p1 ? ff02h port 2 p2 ? ff04h port 4 p4 ? ff06h port 6 p6 ? ff08h port 8 p8 ? 00h ff20h port mode register 0 pm0 ? ff21h port mode register 1 pm1 ? ff22h port mode register 2 pm2 ? ff24h port mode register 4 pm4 ? ff26h port mode register 6 pm6 ? ffh ff28h port mode register 8 pm8 ? 3fh ff32h pull-up resistor option register b2 pub2 ? ff42h watchdog timer clock selection register tcl2 ? ? ff4ah watch timer mode control register wtm ? ff58h port function register 8 pf8 r/w ? 00h ff63h 8-bit compare register 30 cr30 w ? ? undefined ff64h 8-bit timer counter 30 tm30 r ? ? ff65h 8-bit timer mode control register 30 tmc30 r/w ? 00h ff66h 8-bit compare register 40 cr40 ? ? ff67h 8-bit h width compare register 40 crh40 w ? ? undefined ff68h 8-bit timer counter 40 tm40 r ? ? ff69h 8-bit timer mode control register 40 tmc40 r/w ? ff6ah carrier generator output control register 40 tca40 w ? ? ff72h serial operation mode register 10 note1 csim10 note1 ? 00h ff74h transmission/recept ion shift register 10 note1 sio10 note1 ? undefined ffb0h lcd display mode register 0 lcdm0 ? ffb2h lcd clock control register 0 lcdc0 ? 00h ffddh power-on-clear register 1 pocf1 r/w ? 00h note2 notes 1. provided in pd78f9328 only. do not access this address for a mask rom version. 2. this value is 04h only after a power-on-clear reset.
chapter 3 cpu architecture user?s manual u16995ej2v0ud 47 table 3-3. special function registers (2/2) bit unit for manipulation address special function regist er (sfr) name symbol r/w 1 bit 8 bits 16 bits after reset ffe0h interrupt request flag register 0 if0 ? 00h ffe4h interrupt mask flag register 0 mk0 ? ffh ffech external interrupt mode register 0 intm0 ? fff0h suboscillation mode register sckm ? fff2h subclock control register css ? fff5h key return mode register 00 krm00 ? fff7h pull-up resistor option register 0 pu0 ? fff9h watchdog timer mode register wdtm ? 00h fffah oscillation stabilization time selection register osts ? 04h fffbh processor clock control register pcc r/w ? 02h
chapter 3 cpu architecture 48 user?s manual u16995ej2v0ud 3.3 instruction address addressing an instruction address is determined by the program counter (p c) contents. the pc contents are normally incremented (+1 for each byte) automatically according to the number of bytes of an in struction to be fetched each time another instruction is ex ecuted. when a branch instruct ion is executed, the branch destination information is set to the pc and branched by the following addressing (f or details of each instruction, refer to 78k/0s series instructions user?s manual (u11047e) ). 3.3.1 relative addressing [function] the value obtained by adding 8-bit immedi ate data (displacement value: jdis p8) of an instruction code to the start address of the following instruction is transfe rred to the program counter (pc) and branched. the displacement value is treated as signed two?s comple ment data (?128 to +127) and bit 7 becomes a sign bit. this means that information is relatively branched to a location between ?128 and +127, from the start address of the next instruction when relative addressing is used. this function is carried out when the br $addr16 instruct ion or a conditional branch instruction is executed. [illustration] 15 0 pc 15 0 s 15 0 pc + 876 jdisp8 when s = 0, indicates all bits 0. ... pc is the start address of the next instruction of a br instruction. when s = 1, indicates all bits 1.
chapter 3 cpu architecture user?s manual u16995ej2v0ud 49 3.3.2 immediate addressing [function] immediate data in the instructi on word is transferred to the pr ogram counter (pc) and branched. this function is carried out when the call !addr 16 or br !addr16 instru ction is executed. call !addr16 and br !addr16 instruct ions can be branched to any location in the memory space. [illustration] in case of call !addr16 and br !addr16 instructions 15 0 pc 87 70 call or br low addr. high addr.
chapter 3 cpu architecture 50 user?s manual u16995ej2v0ud 3.3.3 table indirect addressing [function] table contents (branch desti nation address) of the particular locati on to be addressed by the lower 5-bit immediate data of an instru ction code from bit 1 to bit 5 are trans ferred to the program counter (pc) and branched. this function is carried out when the callt [addr5] instructi on is executed. the in struction enables a branch to any location in the memory space by referring to t he addresses stored in the memo ry table at 40h to 7fh. [illustration] 15 1 15 0 pc 70 low addr. high addr. memory (table) effective address + 1 effective address 01 00000000 87 87 65 0 0 0 01 765 10 ta 4?0 instruction code 3.3.4 register addressing [function] the register pair (ax) contents to be specified with an instruction word ar e transferred to the program counter (pc) and branched. this function is carried out when t he br ax instruction is executed. [illustration] 70 rp 07 ax 15 0 pc 87
chapter 3 cpu architecture user?s manual u16995ej2v0ud 51 3.4 operand address addressing the following various methods are available to spec ify the register and memory (addressing) which undergo manipulation during inst ruction execution. 3.4.1 direct addressing [function] the memory indicated with imm ediate data in an instruction wo rd is directly addressed. [operand format] identifier description addr16 label or 16-bit immediate data [description example] mov a, !fe00h; when setting !addr16 to fe00h instruction code 00101001op code 00000000 11111110 00h feh [illustration] 70 op code addr16 (lower) addr16 (higher) memory ? ? ? ? ?
chapter 3 cpu architecture 52 user?s manual u16995ej2v0ud 3.4.2 short direct addressing [function] the memory to be manipulated in the fixed space is di rectly addressed with 8-bit dat a in an instruction word. the fixed space is the 256-byte space fe20h to ff1fh where the addressing is applied. internal high-speed ram and special function registers (sfrs) are mapped at fe20h to feffh and ff00h to ff1fh, respectively. the sfr area (ff00h to ff1fh) where short direct addr essing is applied is a part of the whole sfr area. ports that are frequently accessed in a program and the compare register of the time r counter are mapped in this area, and these sfrs can be manipulat ed with a small number of bytes and clocks. when 8-bit immediate data is at 20h to ffh, bit 8 of an effe ctive address is set to 0. when it is at 00h to 1fh, bit 8 is set to 1. see [illustration] below. [operand format] identifier description saddr label or fe20h to ff1fh immediate data saddrp label or fe20h to ff1fh i mmediate data (even address only) [description example] mov fe90h, #50h; when setting saddr to fe90h and the immediate data to 50h instruction code 1 1110101 10010000 01010000 op code 90h (saddr-offset) 50h (immediate data) [illustration] 15 0 short direct memory effective address 1 111111 8 0 7 op code saddr-offset when 8-bit immediate data is 20h to ffh, = 0. when 8-bit immediate data is 00h to 1fh, = 1.
chapter 3 cpu architecture user?s manual u16995ej2v0ud 53 3.4.3 special function register (sfr) addressing [function] the memory-mapped special function registers (sfrs) are addressed with 8-bit immediate data in an instruction word. this addressing is applied to the 256-byte space ff00h to ffffh. however, the sfrs mapped at ff00h to ff1fh can also be accessed with short direct addressing. [operand format] identifier description sfr special function register name [description example] mov pm0, a; when selecting pm0 for sfr instruction code 11100111 00100000 [illustration] 15 0 sfr effective address 1 111111 87 0 7 op code sfr-offset 1
chapter 3 cpu architecture 54 user?s manual u16995ej2v0ud 3.4.4 register addressing [function] in the register addressing mode, general-purpose registers are access ed as operands. the general-purpose register to be accessed is specified by a register specification code or f unctional name in the instruction code. register addressing is carried out when an instruction with the following operand forma t is executed. when an 8-bit register is specified, one of the eight registers is specified wit h 3 bits in the instruction code. [operand format] identifier description r x, a, c, b, e, d, l, h rp ax, bc, de, hl r and rp can be described with absolute names (r0 to r7 and rp0 to rp3) as well as function names (x, a, c, b, e, d, l, h, ax, bc, de, and hl). [description example] mov a, c; when selecting the c register for r instruction code 0 0 001010 00100101 register specification code incw de; when selecting the de register pair for rp instruction code 1 0001000 register specification code
chapter 3 cpu architecture user?s manual u16995ej2v0ud 55 3.4.5 register indirect addressing [function] in the register indirect addressing m ode, memory is manipulated according to the contents of a register pair specified as an operand. the r egister pair to be accessed is specified by the register pair s pecification code in an instruction code. this addressing can be carried out for all the memory spaces. [operand format] identifier description ? [de], [hl] [description example] mov a, [de]; when selecting register pair [de] instruction code 00101011 [illustration] 15 0 8 d 7 e 0 7 7 0 a de addressed memory contents are transferred. memory address specified with register pair de.
chapter 3 cpu architecture 56 user?s manual u16995ej2v0ud 3.4.6 based addressing [function] 8-bit immediate data is added to the cont ents of the base register, that is, t he hl register pair, and the sum is used to address the memory. addition is performed by expanding the offset data as a positive number to 16 bits. a carry from the 16th bit is ignored. this addressing can be carried out for all the memory spaces. [operand format] identifier description ? [hl+byte] [description example] mov a, [hl+10h]; when setting byte to 10h instruction code 00101101 00010000 3.4.7 stack addressing [function] the stack area is indirectly addressed with the stack pointer (sp) contents. this addressing method is automatic ally employed when the push, po p, subroutine call, and return instructions are executed or t he register is saved/restored upon generation of an interrupt request. only the internal high-speed ram area can be addressed using stack addressing. [description example] in the case of push de instruction code 10101010
user?s manual u16995ej2v0ud 57 chapter 4 port functions 4.1 port functions the pd179327 subseries provide the ports shown in figure 4-1, enabling various methods of control. numerous other functions are provi ded that can be used in addition to the digital i/o port functions. for more information on these additional functions, see chapter 2 pin functions . figure 4-1. port types p40 p00 p03 port 0 port 1 p10 port 4 p43 p11 port 2 p20 p22 port 6 p60 p61 p80 port 8 p85
chapter 4 port functions 58 user?s manual u16995ej2v0ud table 4-1. port functions port name pin name function port 0 p00 to p03 this is an i/o port for whic h input and output can be s pecified in 1-bit units. when used as an input port, on-chip pull-up resistors can be specified using pull-up resistor option register 0 (pu0). port 1 p10, p11 this is an i/o port for which input and output can be specified in 1-bit units. when used as an input port, on-chip pull-up resistors can be specified using pull-up resistor option register 0 (pu0). port 2 p20 to p22 this is an i/o port for whic h input and output can be s pecified in 1-bit units. on-chip pull-up resistors can be specified us ing pull-up resistor option register b2 (pub2). port 4 p40 to p43 this is an i/o port for whic h input and output can be s pecified in 1-bit units. when used as an input port, on-chip pull-up resistors can be specified using pull-up resistor option register 0 (pu0), or key return mode register 00 (krm00). port 6 p60, p61 this is an i/o port for which input and output can be specified in 1-bit units. port 8 p80 to p85 this is an i/o port for whic h input and output can be s pecified in 1-bit units. 4.2 port configuration the ports include the following hardware. table 4-2. configuration of port item configuration control registers port mode registers (pmm: m = 0 to 2, 4, 6, 8) pull-up resistor option registers (pu0, pub2) port function register 8 (pf8) ports total: 21 (cmos i/o: 21) pull-up resistors total: 13 (software control: 13)
chapter 4 port functions user?s manual u16995ej2v0ud 59 4.2.1 port 0 port 0 is a 4-bit i/o port with an output la tch. it can be specified in the input or output mode in 1-bit units by using the port mode register 0 (pm0). when t he p00 to p03 pins are used as input port pins, on-chip pull-up resistors can be connected in 4-bit units by using pull- up resistor option register 0 (pu0). reset input sets port 0 in the input mode. figure 4-2 shows a block diagram of port 0. figure 4-2. block di agram of p00 to p03 wr pu0 rd wr port wr pm pu00 pm00 to pm03 v dd p-ch p00 to p03 internal bus selector output latch (p00 to p03) pu0: pull-up resistor option register 0 pm: port mode register rd: port 0 read signal wr: port 0 write signal
chapter 4 port functions 60 user?s manual u16995ej2v0ud 4.2.2 port 1 port 1 is a 2-bit i/o port with an output la tch. it can be specified in the input or output mode in 1-bit units by using port mode register 1 (pm1). when usi ng the p10 and p11 pins as input port pins, on-chip pull-up resistors can be connected in 2-bit units by using pull- up resistor option register 0 (pu0). reset input sets port 1 in the input mode. figure 4-3 shows a block diagram of port 1. figure 4-3. block diagram of p10 and p11 wr pu0 rd wr port wr pm pu01 pm10, pm11 v dd p-ch p10, p11 internal bus selector output latch (p10, p11) pu0: pull-up resistor option register 0 pm: port mode register rd: port 1 read signal wr: port 1 write signal
chapter 4 port functions user?s manual u16995ej2v0ud 61 4.2.3 port 2 port 2 is a 3-bit i/o port with an output la tch. it can be specified in the input or output mode in 1-bit units by using port mode register 2 (pm2). on-chip pu ll-up resistors can be connected in 1-bit units by using pull-up resistor option register b2 (pub2) regardless of whether the port is in the i nput or output mode. this port can also be used as serial interface data i/o in the pd78f9328. reset input sets port 2 in the input mode. figures 4-4 to 4-6 show block diagrams of port 2. caution when using the pins of port 2 as the seria l interface, the i/o or output latch must be set according to the function to be used. for how to set the latches, see table 9-2 settings of serial interface 10 operating mode. figure 4-4. block diagram of p20 p20/sck10 note wr pub2 rd wr port wr pm pub20 pm20 v dd p-ch internal bus alternate function output latch (p20) alternate function selector pub2: pull-up resistor option register b2 pm: port mode register rd: port 2 read signal wr: port 2 write signal note sck10 is provided in the pd78f9328 only.
chapter 4 port functions 62 user?s manual u16995ej2v0ud figure 4-5. block diagram of p21 p21/so10 note wr pub2 rd wr port wr pm pub21 pm21 v dd p-ch internal bus output latch (p21) alternate function selector pub2: pull-up resistor option register b2 pm: port mode register rd: port 2 read signal wr: port 2 write signal note so10 is provided in the pd78f9328 only.
chapter 4 port functions user?s manual u16995ej2v0ud 63 figure 4-6. block diagram of p22 p22/si10 note wr pub2 rd wr port wr pm pub22 pm22 v dd p-ch internal bus alternate function output latch (p22) selector pub2: pull-up resistor option register b2 pm: port mode register rd: port 2 read signal wr: port 2 write signal note si10 is provided in the pd78f9328 only.
chapter 4 port functions 64 user?s manual u16995ej2v0ud 4.2.4 port 4 port 4 is a 4-bit i/o port with an output la tch. it can be specified in the input or output mode in 1-bit units by using port mode register 4 (pm4). when usi ng the p40 to p43 pins as input port pins, on-chip pull-up resistors can be connected in 4-bit units by using pull- up resistor option register 0 (pu0). this port is also used as a key return. reset input sets port 4 in the input mode. figure 4-7 shows block diagram of port 4. figure 4-7. block di agram of p40 to p43 wr krm00 v dd p40/kr00 to p43/kr03 wr pu0 rd wr port wr pm pu04 pm40 to pm43 krm000 p-ch internal bus selector output latch (p40 to p43) alternate function krm00: key return mode register 00 pu0: pull-up resistor option register 0 pm: port mode register rd: port 4 read signal wr: port 4 write signal
chapter 4 port functions user?s manual u16995ej2v0ud 65 4.2.5 port 6 port 6 is a 2-bit i/o port with an output la tch. it can be specified in the input or output mode in 1-bit units by using port mode register 6 (pm6). this port is also used as a timer output and external interrupt input. reset input sets port 6 in the input mode. figures 4-8 and 4-9 show block diagrams of port 6. figure 4-8. block diagram of p60 p60/to40 wr port wr pm pm60 rd internal bus selector output latch (p60) alternate function pm: port mode register rd: port 6 read signal wr: port 6 write signal
chapter 4 port functions 66 user?s manual u16995ej2v0ud figure 4-9. block diagram of p61 p61/int rd wr port wr pm pm61 internal bus alternate function selector output latch (p61) pm: port mode register rd: port 6 read signal wr: port 6 write signal
chapter 4 port functions user?s manual u16995ej2v0ud 67 4.2.6 port 8 port 8 is a 6-bit i/o port with an output la tch. it can be specified in the input or output mode in 1-bit units by using port mode register 8 (pm8). this port is also used as a segment output, and can be swit ched to the port function or segment output function in 1-bit units by port function register 8 (pf8). reset input sets port 8 in the input mode. figure 4-10 shows a block diagram of port 8. figure 4-10. block di agram of p80 to p85 p80/s22 to p85/s17 v dd wr port wr pm output latch (p80 to p85) pm80 to pm85 pf80 to pf85 rd alternate function wr pf internal bus selector v lc0 v lc0 level shifter level shifter pf: port function register rd: port 8 read signal wr: port 8 write signal caution when using port 8 as an output port, the high-level output voltage is v lc0 , not v dd . when a high level is output from the output port, pay attention to the current capacity.
chapter 4 port functions 68 user?s manual u16995ej2v0ud 4.3 registers controlling port function the ports are controlled by the follo wing three types of registers. ? port mode registers (pm0 to pm2, pm4, pm6, pm8) ? pull-up resistor option registers (pu0, pub2) ? port function register 8 (pf8) (1) port mode registers (pm0 to pm2, pm4, pm6, pm8) pm0 to pm2, pm4, pm6 and pm8 are used to set port input/output in 1-bit units. the port mode registers are independently set with a 1-bit or 8-bit memory manipulation instruction. reset input sets pm0, pm1, pm2, pm 4, and pm6 to ffh, and pm8 to 3fh. when port pins are used as alternate-function pins, set the port mode register and output latch according to table 4-3. caution as p61 has an alternat e function as external interrupt i nput, when the port function output mode is specified and the output level is cha nged, the interrupt request flag is set. when the output mode is used, therefore, the interr upt mask flag (pmk0) should be preset to 1. figure 4-11. format of port mode register symbol 7 6 5 4 3 2 1 0 address after reset r/w pm0 1 1 1 1 pm03 pm02 pm01 pm00 ff20h ffh r/w pm1 1 1 1 1 1 1 pm11 pm10 ff21h ffh r/w pm2 1 1 1 1 1 pm22 pm21 pm20 ff22h ffh r/w pm4 1 1 1 1 pm43 pm42 pm41 pm40 ff24h ffh r/w pm6 1 1 1 1 1 1 pm61 pm60 ff26h ffh r/w pm8 0 0 pm85 pm84 pm83 pm82 pm81 pm80 ff28h 3fh r/w pmmn pmn pin input/output mode selection (m = 0 to 2, 4, 6, 8 n = 0 to 5) 0 output mode (output buffer on) 1 input mode (output buffer off) cautions 1. bits 4 to 7 of pm0, bits 2 to 7 of pm1, bits 3 to 7 of pm2, bi ts 4 to 7 of pm4, and bits 2 to 7 of pm6 must be set to 1. 2. bits 6 and 7 of pm8 must be set to 0.
chapter 4 port functions user?s manual u16995ej2v0ud 69 table 4-3. port mode registers and output latch settings when us ing alternate functions alternate function pin name name i/o pm p input 1 p20 sck10 note1 output 0 1 p21 so10 note1 output 0 1 p22 si10 note1 input 1 p40 to p43 kr00 to kr03 input 1 p60 to40 output 0 0 p61 int input 1 p80 to p85 s22 to s17 note2 output notes 1. the pd78f9328 only 2. when using p80 to p85 pins as s22 to s17, set port function register 8 (pf8) to 3fh. caution when port 2 is used as a serial interface pin, the i/o latch or output latch must be set according to its function. for the setting method, see tabl e 9-2 settings of serial interface 10 operating mode. remark : don?t care pm : port mode register p : port output latch (2) pull-up resistor option register 0 (pu0) pu0 sets whether an on-chip pull-up resistor on ports 0, 1, and 4 is used or not in port units. on the port specified to use an on-chip pull-up resi stor by pu0, the pull-up resistor c an be internally used only for the bits set in the input mode. no on-chip pull-up resistors c an be used for the bits set in the output mode regardless of the setting of pu0. this also applies to ca ses when the pins are used for alternate functions. pu0 is set with a 1-bit or 8-bit memory manipulation instruction. reset input clears pu0 to 00h. figure 4-12. format of pull-up resistor option register 0 symbol 7 6 5 <4> 3 2 <1> <0> address after reset r/w pu0 0 0 0 pu04 0 0 pu01 pu00 fff7h 00h r/w pu0m pm on-chip pull-up resistor selection (m = 0, 1, 4) 0 on-chip pull-up resistor not used 1 on-chip pull-up resistor used caution bits 2, 3, and 5 to 7 must be set to 0.
chapter 4 port functions 70 user?s manual u16995ej2v0ud (3) pull-up resistor option register b2 (pub2) pub2 sets whether on-chip pull-up resistors on p20 to p 22 are used or not in bit units. a pin for which use of an on-chip pull-up resistor is specified by pub2 c an be connected to the pull-up resistor regardless of whether the pin is in the input or output mode. the same applies when the alternat e function of the pin is used. pub2 is set with a 1-bit or 8-bit memory manipulation instruction. reset input clears pub2 to 00h. figure 4-13. format of pull-up resistor option register b2 symbol 7 6 5 4 3 <2> <1> <0> address after reset r/w pub2 0 0 0 0 0 pub22 pub21 pub20 ff32h 00h r/w pub2n p2n on-chip pull-up resistor selection (n = 0 to 2) 0 on-chip pull-up resistor not connected 1 on-chip pull-up resistor connected cautions 1. bits 3 to 7 must be set to 0. 2. clear pub2n to 0 when using p2n in the out put mode or using it as an alternate function output pin. otherwise, it always outputs a high level. (4) port function register 8 (pf8) pf8 sets the port function of port 8 in 1-bit units. the pins of port 8 are selected as either lcd segment signal outputs or general-purpose port pins according to the setting of pf8. pf8 is set with a 1-bit or 8-bit memory manipulation instruction. reset input clears pf8 to 00h.
chapter 4 port functions user?s manual u16995ej2v0ud 71 figure 4-14. format of port function register 8 symbol 7 6 5 4 3 2 1 0 address after reset r/w pf8 0 0 pf85 pf84 pf83 pf82 pf81 pf80 ff58h 00h r/w pf8n p8n port function (n = 0 to 5) 0 operates as a general-purpose port 1 operates as an lcd segment signal output cautions 1. bits 6 and 7 must be set to 0. 2. when port 8 is used as a general-pur pose port, observe the following restriction (because an esd protection circui t for lcd pins (on the high-level side of port 8) is connected to v lc0 ). ? when any one of pins p80/s22 to p85/s 17 is used as a general-purpose input port pin, use the microcontroller at v dd = v lc0 or v dd < v lc0 . there is no restriction when all of pins p80/s22 to p85/s17 ar e used as lcd segment pins or general-purpo se output port pins. p8n/sm sm output signal p8n input signal v dd v ss pf8n v ss v lc0 rd p-ch pm8n v lc0 n-ch v ss p8n output signal segment buffer if a voltage higher than v lc0 is input to the p8n/sm pin, the current flows from the pin to v lc0 . as a result, the voltage of v lc0 becomes unstable. remark sm: lcd segment output (m = 22 to 17) p8n: bit n of port 8 (n = 0 to 5) pf8n: bit n of port function register 8 (n = 0 to 5) rd: port 8 read signal
chapter 4 port functions 72 user?s manual u16995ej2v0ud 4.4 port function operation the operation of a port differs depending on whether the port is set in the input or output m ode, as described below. 4.4.1 writing to i/o port (1) in output mode a value can be written to the output la tch of a port by using a transfer inst ruction. the cont ents of the output latch can be output from the pins of the port. data once written to the output latch is retai ned until new data is writt en to the output latch. (2) in input mode a value can be written to the output latc h by using a transfer instruction. however, the status of the port pin is not changed because the out put buffer is off. data once written to the output latch is retai ned until new data is writt en to the output latch. caution a 1-bit memory manipulation instruction is executed to manipulate 1 bit of a port. however, this instruction accesses th e port in 8-bit units. when this instruction is executed to manipulate a bit of an input/output port, theref ore, the contents of the output latch of the pin that is set in the input mode and not subject to manipulation become undefined. 4.4.2 reading from i/o port (1) in output mode the status of an output latc h can be read by using a transfer instructi on. the contents of the output latch are not changed. (2) in input mode the status of a pin can be read by using a transfer instruction. the contents of the output latch are not changed. 4.4.3 arithmetic operation of i/o port (1) in output mode an arithmetic operation can be performed with the contents of the output latch. the re sult of the operation is written to the output latch. the contents of the out put latch are output from the port pins. data once written to the output latch is retai ned until new data is writt en to the output latch. (2) in input mode the contents of the output latch become undefined. however, the status of the pin is not changed because the output buffer is off. caution a 1-bit memory manipulation instruction is executed to manipulate 1 bit of a port. however, this instruction accesses th e port in 8-bit units. when this instruction is executed to manipulate a bit of an input/output port, theref ore, the contents of the output latch of the pin that is set in the input mode and not subject to manipulation become undefined.
user?s manual u16995ej2v0ud 73 chapter 5 clock generator 5.1 clock generator functions the clock generator generates the clock to be supplied to the cpu and peripheral hardware. the following two types of system clock oscillators are used. ? main system clock (cer amic/crystal) oscillator this circuit oscillates at 1.0 to 5.0 mhz. oscillati on can be stopped by executing the stop instruction or setting the processor clock control register (pcc). ? subsystem clock oscillator this circuit oscillates at 32.768 khz. oscillation can be stopped by the suboscilla tion mode register (sckm). 5.2 clock generator configuration the clock generator includes the following hardware. table 5-1. configuration of clock generator item configuration control registers processor cl ock control register (pcc) suboscillation mode register (sckm) subclock control register (css) oscillators main system clock oscillator subsystem clock oscillator
chapter 5 clock generator 74 user?s manual u16995ej2v0ud figure 5-1. block diag ram of clock generator subsystem clock oscillator f xt x1 x2 xt1 xt2 main system clock oscillator f x f x 2 2 f xt 2 1/2 prescaler watch timer lcd controller/driver clock to peripheral hardware cpu clock (f cpu ) standby controller wait controller stop mcc pcc1 cls css0 internal bus suboscillation mode register (sckm) frc scc internal bus subclock control register (css) processor clock control register (pcc) selector
chapter 5 clock generator user?s manual u16995ej2v0ud 75 5.3 registers controlling clock generator the clock generator is controlled by the following three registers. ? processor clock control register (pcc) ? suboscillation mode register (sckm) ? subclock control register (css) (1) processor clock control register (pcc) pcc sets cpu clock selection and the division ratio. pcc is set with a 1-bit or 8-bit me mory manipulation instruction. reset input sets pcc to 02h. figure 5-2. format of processo r clock control register symbol <7> 6 5 4 3 2 1 0 address after reset r/w pcc mcc 0 0 0 0 0 pcc1 0 fffbh 02h r/w mcc control of main system clock oscillator operation 0 operation enabled 1 operation disabled maximum instruction execution time: 2/f cpu css0 pcc1 cpu clock (f cpu ) selection note f x = 5.0 mhz or f xt = 32.768 khz operation 0 0 f x 0.4 s 0 1 f x /2 2 1.6 s 1 f xt /2 122 s note the cpu clock is selected according to a combinati on of the pcc1 flag in the processor clock control register (pcc) and the css0 flag in the s ubclock control register (css) (refer to 5.3 (3) subclock control register (css) ). cautions 1. bits 0 and 2 to 6 must be set to 0. 2. the mcc can be set only when the s ubsystem clock has been selected as the cpu clock. setting mcc to 1 while the main system clock is operating is invalid. remarks 1. f x : main system clock oscillation frequency 2. f xt : subsystem clock oscillation frequency 3. : don?t care
chapter 5 clock generator 76 user?s manual u16995ej2v0ud (2) suboscillation mode register (sckm) sckm selects a feedback resistor for the subsystem clock, and controls the o scillation of the clock. sckm is set with a 1-bit or 8-bit memory manipulation instruction. reset input clears sckm to 00h. figure 5-3. format of s uboscillation mode register symbol 7 6 5 4 3 2 1 0 address after reset r/w sckm 0 0 0 0 0 0 frc scc fff0h 00h r/w frc feedback resistor selection note 0 on-chip feedback resistor used 1 on-chip feedback resistor not used scc control of subsystem clock oscillator operation 0 operation enabled 1 operation disabled note the feedback resistor is necessary to adjust the bias point of the oscillation waveform to close to the mid point of the supply voltage. only when the subclock is not used, the power consumption in stop mode can be further reduced by setting frc = 1. caution bits 2 to 7 must be set to 0. (3) subclock control register (css) css specifies whether the main system or subsystem clock oscillator is to be selected. it also specifies the cpu clock operation status. css is set with a 1-bit or 8-bit memory manipulation instruction. reset input clears css to 00h. figure 5-4. format of subclock control register symbol 7 6 5 4 3 2 1 0 address after reset r/w css 0 0 cls css0 0 0 0 0 fff2h 00h r/w note cls cpu clock operation status 0 operation based on the output of the divided main system clock 1 operation based on the subsystem clock css0 selection of the main system or subsystem clock oscillator 0 divided output from the main system clock oscillator 1 output from the subsystem clock oscillator note bit 5 is read only. caution bits 0 to 3, 6, and 7 must be set to 0.
chapter 5 clock generator user?s manual u16995ej2v0ud 77 5.4 system clock oscillators 5.4.1 main system clock oscillator the main system clock oscillator is oscillated by the crystal or ceramic resonator (5.0 mhz typ.) connected across the x1 and x2 pins. an external clock can also be input to the circuit. in th is case, input the clock signal to the x1 pin, and input the inverted signal to the x2 pin. figure 5-5 shows the external circuit of the main system clock oscillator. figure 5-5. external circuit of main system clock oscillator (a) crystal or ceramic osc illation (b) external clock crystal or ceramic resonator v ss x2 x1 external clock x1 x2 caution when using the main system or subsystem cl ock oscillator, wire as follo ws in the area enclosed by the broken lines in figures 5-5 and 5-6 to avo id an adverse effect fr om wiring capacitance. ? keep the wiring length as short as possible. ? do not cross the wiring with the other signal lin es. do not route the wiring near a signal line through which a high fluctuating current flows. ? always make the ground point of the osc illator capacitor the same potential as v ss . do not ground the capacitor to a ground pattern through which a high current flows. ? do not fetch signals from the oscillator.
chapter 5 clock generator 78 user?s manual u16995ej2v0ud 5.4.2 subsystem clock oscillator the subsystem clock oscillator is oscillated by the cr ystal resonator (32.768 khz t yp.) connected across the xt1 and xt2 pins. an external clock can also be input to the circuit. in th is case, input the clock signal to the xt1 pin, and input the inverted signal to the xt2 pin. figure 5-6 shows the external circuit of the subsystem clock oscillator. figure 5-6. external circuit of subsystem clock oscillator (a) crystal oscillation (b) external clock xt2 v ss xt1 32.768 khz crystal resonator external clock xt1 xt2 caution when using the main system or subsystem cl ock oscillator, wire as follo ws in the area enclosed by the broken lines in figures 5-5 and 5-6 to avo id an adverse effect fr om wiring capacitance. ? keep the wiring length as short as possible. ? do not cross the wiring with the other signal lin es. do not route the wiring near a signal line through which a high fluctuating current flows. ? always make the ground point of the osc illator capacitor the same potential as v ss . do not ground the capacitor to a ground pattern through which a high current flows. ? do not fetch signals from the oscillator. when using the subsystem cl ock, particular care is requi red because the s ubsystem clock oscillator is designed as a low-amplitude ci rcuit for reducing cu rrent consumption.
chapter 5 clock generator user?s manual u16995ej2v0ud 79 5.4.3 example of incorr ect resonator connection figure 5-7 shows examples of incorrect resonator connection. figure 5-7. examples of incorr ect resonator connection (1/2) (a) too long wiring (b) crossed signal line v ss x1 x2 v ss x1 x2 portn (n = 0 to 2, 4, 6, 8) (c) wiring near high fluctuating current (d) current flowing through ground line of oscillator (potential at points a, b, and c fluctuates) v ss x1 x2 high current v ss x1 ab c p mn v dd high current x2 remark when using the subsystem clock, read x1 and x2 as xt1 and xt2, re spectively, and connect a resistor to the xt2 in series.
chapter 5 clock generator 80 user?s manual u16995ej2v0ud figure 5-7. examples of incorr ect resonator connection (2/2) (e) signal is fetched (f) parallel and near signal lines of main system clock and subsystem clock v ss x1 x2 v ss x2 xt2 is wired parallel to x1. x1 xt2 xt1 remark when using the subsystem clock, read x1 and x2 as xt1 and xt2, re spectively, and connect a resistor to the xt2 in series. caution if the x1 wire is in para llel with the xt2 wire, crosstalk noise may occur between the x1 and xt2, resulting in a malfunction. to avoid this, do not lay the x1 and xt2 wires in parallel. 5.4.4 divider circuit the divider circuit divides the output of the main system clock oscillator (f x ) to generate various clocks. 5.4.5 when no subsyst em clock is used if a subsystem clock is not necessary, for example, fo r low-power consumption oper ation or clock operation, handle the xt1 and xt2 pins as follows: xt1: connect to v ss xt2: leave open in this case, however, a small current leaks via the on- chip feedback resistor in the subsystem clock oscillator when the main system clock is stopped. to avoid this, set bit 1 (frc) of the suboscilla tion mode register (sckm) so that the on-chip feedback resistor will not be used. also in this case, handle the xt1 and xt2 pins as stated above.
chapter 5 clock generator user?s manual u16995ej2v0ud 81 5.5 clock generator operation the clock generator generates the following clocks and controls the operat ion modes of the cpu, such as the standby mode. ? main system clock f x ? subsystem clock f xt ? cpu clock f cpu ? clock to peripheral hardware the operation and function of the clock generator is dete rmined by the processor clock control register (pcc), suboscillation mode register (sckm), and subclo ck control register (css), as follows. (a) the low-speed mode (1.6 s: at 5.0 mhz operation) of the ma in system clock is selected when the reset signal is generated (pcc = 02h). while a low leve l is input to the reset pin, oscillation of the main system clock is stopped. (b) three types of minimum instruction execution time (0.4 s and 1.6 s: main system clock (at 5.0 mhz operation), 122 s: subsystem clock (at 32.768 khz operati on)) can be selected by the pcc, sckm, and css settings. (c) two standby modes, stop and halt , can be used with the main system clock selected. in a system where no subsystem clock is used, setting bit 1 (f rc) of the sckm so t hat the on-chip feedback resistor cannot be used reduces curr ent consumption in stop mode. in a system where a subsystem clock is used, setting sckm bit 0 to 1 can c ause the subsystem clock to stop oscillation. (d) css bit 4 (css0) can be used to select the subsyst em clock so that low cu rrent consumption operation is used (122 s: at 32.768 khz operation). (e) with the subsystem clock selected, it is possibl e to cause the main system clock to stop oscillating using bit 7 (mcc) of pcc. the halt mode can be used, but the stop mode cannot. (f) the clock pulse for the peripheral hardware is generated by dividing the fr equency of the main system clock, but the subsystem clock pulse is only suppli ed to the watch timer and lcd controller/driver. the watch timer and lcd controller/driver can ther efore keep running even dur ing standby. the other hardware stops when the main syst em clock stops because it runs based on the main system clock (except for external input clock operations).
chapter 5 clock generator 82 user?s manual u16995ej2v0ud 5.6 changing setting of s ystem clock and cpu clock 5.6.1 time required for switching between system clock and cpu clock the cpu clock can be selected by using bit 1 (pcc1) of the processor clock control register (pcc) and bit 4 (css0) of the subclock control register (css). the maximum time indicated in table 5- 2 is required until the cpu clock actua lly switches (i.e. switching does not occur immediately after the pcc register is rewritten). un til this time has elapsed, ther efore, it is impossible to ascertain whether the clock before or after the switch is operating. table 5-2. maximum time re quired for switching cpu clock set value before switching set value after switching css0 pcc1 css0 pcc1 css0 pcc1 css0 pcc1 0 0 0 1 1 0 0 4 clocks 2f x /f xt clocks (306 clocks) 1 2 clocks f x /2f xt clocks (76 clocks) 1 2 clocks 2 clocks remarks 1. two clocks are the minimum instruction execut ion time of the cpu clock before switching. 2. the parenthesized values apply to operation at f x = 5.0 mhz or f xt = 32.768 khz. 3. : don?t care
chapter 5 clock generator user?s manual u16995ej2v0ud 83 5.6.2 switching between system clock and cpu clock the following figure illustrates how t he cpu clock and system clock switch. figure 5-8. example of switching between system clock and cpu clock system clock cpu clock input request signal reset v dd f x f x f xt f x low-speed operation high-speed operation subsystem clock operation high-speed operation oscillation stabilization time wait (6.55 ms at 5.0 mhz operation) internal reset operation pcc rewrite few clocks (for maximum values, refer to table 5-2 .) css rewrite css rewrite <1> the cpu is reset when the reset pin is made low on pow er application. the effect of resetting is released when the reset pin is later made high, and the main syst em clock starts oscillating. at this time, the oscillation stabilization time (2 15 /f x ) is automatically secured. after that, the cpu starts inst ruction execution at the slow s peed of the main system clock (1.6 s at 5.0 mhz operation). <2> after the time required for the v dd voltage to rise to the level at which the cpu can operate at high speed has elapsed, bit 1 (pcc1) of the processor cl ock control register (pcc) is rewritten. <3> after a few clocks have elapsed, the cp u clock is switched to high-speed (0.4 s at 5.0 mhz operation), and the cpu starts the high-speed operation. <4> a drop of the v dd voltage is detected by an inte rrupt request signal. bit 4 (css0) of the subclock control register (css) is rewritten so t hat the clock is switched to the s ubsystem clock (at this moment, the subsystem clock must be in t he oscillation stabilized status). <5> after a few clocks have elapsed, the cpu clock is switched to the sub system clock operation (122 s at 32.768 khz operation). (at this time, bit 7 (mcc) of pcc can be set to 1 to stop the main system clock.) <6> when a recover of the v dd voltage is detected by an in terrupt request signal, css0 is written so that the cpu clock is switched to the main system clock. ( if the main system clock is stopped, set bit 7 (mcc) of pcc to 0 so that the main system clock starts oscilla ting. after the time required for the oscillation to stabilize has elapsed, rewrite css0.) <7> after a few clocks, the cpu clock is switched to high speed (0.4 s at 5.0 mhz operation), and the cpu returns to high-speed operation. caution when the main system clock is stoppe d and the device is operating on the subsystem clock, wait until the oscillation stabilization ti me has been secured by the program before switching back to the main system clock.
84 user?s manual u16995ej2v0ud chapter 6 8-bit timers 30 and 40 6.1 8-bit timers 30 and 40 functions the 8-bit timer in the pd179327 subseries has 2 channels (timer 30 and timer 40). the operation modes listed in the following table can be set via mode register settings. table 6-1. operation modes channel mode timer 30 timer 40 8-bit timer counter mode (discrete mode) available available 16-bit timer counter mode (cascade connection mode) available carrier generator mode available pwm output mode not available available (1) 8-bit timer counter mode (discrete mode) the following functions can be used in this mode. ? interval timer with 8-bit resolution ? square-wave output with 8-bi t resolution (timer 40 only) (2) 16-bit timer counter m ode (cascade connection mode) operation as a 16-bit timer is enabled during cascade connection mode. the following functions can be used in this mode. ? interval timer with 16-bit resolution ? square-wave output with 16-bit resolution (3) carrier generator mode the carrier clock generated by timer 40 is output in cycles set by timer 30. (4) pwm output mode (timer 40 only) pulses are output using any duty factor set by timer 40.
chapter 6 8-bit timers 30 and 40 user?s manual u16995ej2v0ud 85 6.2 8-bit timers 30 and 40 configuration the 8-bit timers 30 and 40 include the following hardware. table 6-2. configuration of 8-bit timers 30 and 40 item configuration timer counters 8 bits 2 (tm30, tm40) registers compare registers: 8 bits 3 (cr30, cr40, crh40) timer outputs 1 (to40) control registers 8-bit timer mode control register 30 (tmc30) 8-bit timer mode control register 40 (tmc40) carrier generator output control register 40 (tca40) port mode register 6 (pm6) port 6 (p6)
chapter 6 8-bit timers 30 and 40 86 user?s manual u16995ej2v0ud figure 6-1. block diagram of timer 30 tce30 tcl300 tmd300 tcl301 8-bit timer mode control register 30 (tmc30) selector decoder selector selector 8-bit compare register 30 (cr30) 8-bit timer counter 30 (tm30) selector internal reset signal timer 40 match signal (in cascade connection mode) timer 30 match signal (in cascade connection mode) from figure 6-2 (d) count operation start signal (for cascade connection) inttm30 f x /2 6 f x /2 8 timer 40 interrupt request signal (from figure 6-2 (b) ) carrier clock (from figure 6-2 (c) ) clear cascade connection mode match from figure 6-2 (e) to figure 6-2 (f) to figure 6-2 (g) internal bus ovf timer 30 match signal (in carrier generator mode) bit 7 of tm40 (from figure 6-2 (a) ) (a) (g) (b) (c) (d) (e) (f)
chapter 6 8-bit timers 30 and 40 user?s manual u16995ej2v0ud 87 figure 6-2. block diagram of timer 40 tce40 tcl402 tcl401 tcl400 tmd401 tmd400 toe40 8-bit timer mode control register 40 (tmc40) decoder 8-bit timer counter 40 (tm40) f/f tm30 match signal (in cascade connection mode) count operation start signal to timer 30 (in cascade connection mode) tm40 timer counter match signal (in cascade connection mode) clear f x f x /2 2 8-bit compare register 40 (cr40) selector output controller note rmc40 nrzb40 nrz40 carrier generator output control register 40 (tca40) to figure 6-1 (d) count clock input signal to tm30 internal reset signal inttm40 bit 7 of tm40 (in cascade connection mode) to figure 6-1 (a) to figure 6-1 (f) to figure 6-1 (e) match to40/p60 (g) (c) (a) (b) (f) (d) (e) to figure 6-1 (c) carrier clock reset carrier generator mode pwm mode cascade connection mode note refer to figure 6-3 for details. 8-bit h width compare register 40 (crh40) internal bus selector ovf prescaler f x /2 f x /2 2 f x /2 3 f x /2 4 timer 40 interrupt request signal to figure 6-1 (b) timer counter match signal from timer 30 (in carrier generator mode) from figure 6-1 (g)
chapter 6 8-bit timers 30 and 40 88 user?s manual u16995ej2v0ud figure 6-3. block diagram of output controller (timer 40) f/f rmc40 nrz40 toe40 pm60 p60 output latch selector to40/p60 carrier generator mode carrier clock (1) 8-bit compare register 30 (cr30) this 8-bit register is used to continually compare t he value set to cr30 with the count value in 8-bit timer counter 30 (tm30) and to generate an interrupt request (inttm30) when a match occurs. cr30 is set with an 8-bit memory manipulation instruction. reset input makes cr30 undefined. caution cr30 cannot be used in pwm output mode. (2) 8-bit compare register 40 (cr40) this 8-bit register is used to continually compare t he value set to cr40 with the count value in 8-bit timer counter 40 (tm40) and to generate an interrupt request (inttm40) when a match occurs. when connected to tm30 via a cascade connection and used as a 16-bit ti mer, the interrupt request (inttm40) occurs only when matches occur simultaneously between cr30 and tm30 and between cr40 and tm40 (inttm30 does not occur). in carrier generator mode or pwm output mode, cr40 sets the timer output low-level width. cr40 is set with an 8-bit memory manipulation instruction. reset input makes cr40 undefined. (3) 8-bit h width compar e register 40 (crh40) in carrier generator mode or pwm output mode, the high-level width of time r output is set by writing a value to crh40. the set value of crh40 is always compared with the tm 40 count value, and when t hey match, an interrupt request (inttm40) is generated. crh40 is set with an 8-bit memory manipulation instruction. reset input makes crh40 undefined.
chapter 6 8-bit timers 30 and 40 user?s manual u16995ej2v0ud 89 (4) 8-bit timer counters 30 and 40 (tm30 and tm40) these are 8-bit registers that ar e used to count the count pulse. tm30 and tm40 are read with an 8-bit me mory manipulation instruction. reset input sets tm30 and tm40 to 00h. tm30 and tm40 are cleared to 00h under the following conditions. (a) discrete mode (i) tm30 ? after reset ? when tce30 (bit 7 of 8-bit timer mode c ontrol register 30 (tmc30)) is cleared to 0 ? when a match occurs between tm30 and cr30 ? when the tm30 count value overflows (ii) tm40 ? after reset ? when tce40 (bit 7 of 8-bit timer mode c ontrol register 40 (tmc40)) is cleared to 0 ? when a match occurs between tm40 and cr40 ? when the tm40 count value overflows (b) cascade connection mode (tm30 and tm 40 are simultaneously cleared to 00h) ? after reset ? when the tce40 flag is cleared to 0 ? when matches occur simultaneously bet ween tm30 and cr30 and between tm40 and cr40 ? when the tm30 and tm40 count va lues overflow simultaneously (c) carrier generator mode/p wm output mode (tm40 only) ? after reset ? when the tce40 flag is cleared to 0 ? when a match occurs between tm40 and cr40 ? when a match occurs between tm40 and crh40 ? when the tm40 count value overflows
chapter 6 8-bit timers 30 and 40 90 user?s manual u16995ej2v0ud 6.3 registers controlling 8-bit timers 30 and 40 8-bit timer 30 and 40 are controlled by the following five registers. ? 8-bit timer mode control register 30 (tmc30) ? 8-bit timer mode control register 40 (tmc40) ? carrier generator output c ontrol register 40 (tca40) ? port mode register 6 (pm6) ? port 6 (p6)
chapter 6 8-bit timers 30 and 40 user?s manual u16995ej2v0ud 91 (1) 8-bit timer mode control register 30 (tmc30) 8-bit timer mode control register 30 (tmc30) is us ed to control the timer 30 count clock setting and the operation mode setting. tmc30 is set with a 1-bit or 8-bit memory manipulation instruction. reset input sets tmc30 to 00h. figure 6-4. format of 8-bit timer mode control register 30 symbol <7> 6 5 4 3 2 1 0 address after reset r/w tmc30 tce30 0 0 tcl301 tcl300 0 tmd300 0 ff65h 00h r/w tce30 control of tm30 count operation note 1 0 clear tm30 count value and stop operation 1 start count operation tcl301 tcl300 selection of timer 30 count clock 0 0 f x /2 6 (78.1 khz) 0 1 f x /2 8 (19.5 khz) 1 0 timer 40 match signal 1 1 carrier clock created for timer 40 tmd300 tmd401 tmd400 selection of operation mode for timer 30 and timer 40 note 2 0 0 0 8-bit timer counter mode (discrete mode) 1 0 1 16-bit timer counter mode (cascade connection mode) 0 1 1 carrier generator mode 0 1 0 timer 40: pwm output mode timer 30: 8-bit timer counter mode other than above setting prohibited notes 1. since the count operation is c ontrolled by tce40 (bit 7 of tm c40) in cascade connection mode, any setting for tce30 is ignored. 2. the operation mode selection is set to bot h the tmc30 register and tmc40 register. cautions 1. in cascade connection mode, the time r 40 output signal is forcibly selected for the count clock. 2. be sure to clear bits 0, 2, 5, and 6 to 0. remarks 1. f x : main system clock oscillation frequency 2. the parenthesized values apply to operation at f x = 5.0 mhz.
chapter 6 8-bit timers 30 and 40 92 user?s manual u16995ej2v0ud (2) 8-bit timer mode control register 40 (tmc40) 8-bit timer mode control register 40 (tmc40) is us ed to control the timer 40 count clock setting and the operation mode setting. tmc40 is set with a 1-bit or 8-bit memory manipulation instruction. reset input sets tmc40 to 00h. figure 6-5. format of 8-bit timer mode control register 40 symbol <7> 6 5 4 3 2 1 <0> address after reset r/w tmc40 tce40 0 tcl402 tcl401 tcl400 tmd401 tmd400 toe40 ff69h 00h r/w tce40 control of tm40 count operation note 1 0 clear tm40 count value and stop operation (the c ount value is also cleared for tm30 during cascade connection mode) 1 start count operation (the count operation is al so started for tm30 during cascade connection mode) tcl402 tcl401 tcl400 selection of timer 40 count clock 0 0 0 f x (5 mhz) 0 0 1 f x /2 2 (1.25 mhz) 0 1 0 f x /2 (2.5 mhz) 0 1 1 f x /2 2 (1.25 mhz) 1 0 0 f x /2 3 (625 khz) 1 0 1 f x /2 4 (313 khz) other than above setting prohibited tmd300 tmd401 tmd400 selection of operation mode for timer 30 and timer 40 note 2 0 0 0 8-bit timer counter mode (discrete mode) 1 0 1 16-bit timer counter mode (cascade connection mode) 0 1 1 carrier generator mode 0 1 0 timer 40: pwm output mode timer 30: 8-bit timer counter mode other than above setting prohibited toe40 control of timer output 0 output disabled (port mode) 1 output enabled notes 1. since the count operation is controlled by tce40 in cascade connection mode, any setting for tce30 (bit 7 of tmc30) is ignored. 2. the operation mode selection is set to bot h the tmc30 register and tmc40 register. caution be sure to clear bit 6 to 0. remarks 1. f x : main system clock oscillation frequency 2. the parenthesized values apply to operation at f x = 5.0 mhz.
chapter 6 8-bit timers 30 and 40 user?s manual u16995ej2v0ud 93 (3) carrier generator output control register 40 (tca40) this register is used to set the time r output data in carrier generator mode. tca40 is set with an 8-bit memo ry manipulation instruction. reset input sets tca40 to 00h. figure 6-6. format of carrier gene rator output control register 40 symbol 7 6 5 4 3 2 1 0 address after reset r/w tca40 0 0 0 0 0 rmc40 nrzb40 nrz40 ff6ah 00h r/w rmc40 control of remote control output 0 when nrz40 = 1, carrier pulse is output to to40/p60 pin 1 when nrz40 = 1, high-level signal is output to to40/p60 pin nrzb40 this is the bit that stores the next data to be out put to nrz40. data is transferred to nrz40 at the rising edge of the timer 30 match signal. input the nece ssary value in nrzb40 in advance by program. nrz40 no return zero data 0 output low-level signal (carrier clock is stopped) 1 output carrier pulse or high-level signal cautions 1. bits 3 to 7 must be set to 0. 2. tca40 cannot be set with a 1-bit memory mani pulation instruction. be sure to use an 8- bit memory manipulation in struction to set tca40. 3. the nrz40 flag can be written only when carrier generator output is stopped (toe40 = 0). the data cannot be o verwritten when toe40 = 1. 4. when the carrier generator is stopped once and then started again, nrzb40 does not hold the previous data. re-set data to nrzb40. at this time, a 1-bit memory manipulation instruction must not be used . be sure to use an 8-bit memory manipulation instruction. 5. to enable operation in the carrier generator mode, set a val ue to the compare registers (cr30, cr40, and crh40), and input th e necessary value to the nrzb40 and nrz40 flags in advance. otherwise, the signal of the timer matc h circuit will become unstable and the nrz40 flag will be undefined.
chapter 6 8-bit timers 30 and 40 94 user?s manual u16995ej2v0ud (4) port mode register 6 (pm6) this register is used to set the i/o mode of port 6 in 1-bit units. when using the p60/to40 pin as a timer outpu t, set the pm60 and p60 output latch to 0. pm6 is set with a 1-bit or 8-bit memory manipulation instruction. reset input sets pm6 to ffh. figure 6-7. format of port mode register 6 symbol 7 6 5 4 3 2 1 0 address after reset r/w pm6 1 1 1 1 1 1 pm61 pm60 ff26h ffh r/w pm6n i/o mode of p6n pin (n = 0, 1) 0 output mode (output buffer is on) 1 input mode (output buffer is off) caution bits 2 to 7 must be set to 1.
chapter 6 8-bit timers 30 and 40 user?s manual u16995ej2v0ud 95 6.4 8-bit timers 30 and 40 operation 6.4.1 operation as 8-bit timer counter timers 30 and 40 can be independently us ed as 8-bit timer counters. the following modes can be used fo r the 8-bit timer counters. ? interval timer with 8-bit resolution ? square-wave output with 8-bi t resolution (timer 40 only) (1) operation as interval timer with 8-bit resolution the interval timer with 8-bit resolution repeatedly generates an interrupt at a time interval specified by the count value preset in 8-bit compare register n0 (crn0). to operate 8-bit timer n0 as an interval timer, settings must be made in the following sequence. <1> disable operation of 8-bit timer counter n0 (tmn0) (tcen0 = 0). <2> disable timer output of ton0 (toen0 = 0). <3> set a count value in crn0. <4> set the operation mode of timer n0 to 8-bit timer counter mode (see figures 6-4 and 6-5 ). <5> set the count clock for timer n0 (see tables 6-3 and 6-4 ). <6> enable the operation of tmn0 (tcen0 = 1). when the count value of 8-bit timer counter n0 (tmn0) matches the val ue set in crn0, tmn0 is cleared to 00h and continues counting. at the same time, an interrupt request signal (inttmn0) is generated. tables 6-3 and 6-4 show the interval time, and figures 6-8 to 6-12 show the timing of the interval timer operation. caution be sure to stop the timer operation before overwriting the count cl ock with different data. remark n = 3, 4
chapter 6 8-bit timers 30 and 40 96 user?s manual u16995ej2v0ud table 6-3. interval time of timer 30 (at f x = 5.0 mhz operation) tcl301 tcl300 minimum interval time ma ximum interval time resolution 0 0 2 6 /f x (12.8 s) 2 14 /f x (3.28 ms) 2 4 /f x (12.8 s) 0 1 2 8 /f x (51.2 s) 2 16 /f x (13.1 ms) 2 8 /f x (51.2 s) 1 0 input cycle of timer 40 match signal input cycle of timer 40 match signal 2 8 input cycle of timer 40 match signal 1 1 carrier clock cycle created with timer 40 carrier clock cycle created with timer 40 2 8 carrier clock cycle created with timer 40 remark f x : main system clock oscillation frequency table 6-4. interval time of timer 40 (at f x = 5.0 mhz operation) tcl402 tcl401 tcl400 minimum interval time maximum interval time resolution 0 0 0 1/f x (0.2 s) 2 8 /f x (51 s) 1/f x (0.2 s) 0 0 1 2 2 /f x (0.8 s) 2 10 /f x (205 s) 2 2 /f x (0.8 s) 0 1 0 2/f x (0.4 s) 2 9 /f x (102 s) 2/f x (0.4 s) 0 1 1 2 2 /f x (0.8 s) 2 10 /f x (205 s) 2 2 /f x (0.8 s) 1 0 0 2 3 /f x (1.6 s) 2 11 /f x (410 s) 2 3 /f x (1.6 s) 1 0 1 2 4 /f x (3.2 s) 2 12 /f x (819 s) 2 4 /f x (3.2 s) remark f x : main system clock oscillation frequency figure 6-8. timing of interval timer oper ation with 8-bit resolution (basic operation) count stop count clock crn0 tcen0 inttmn0 ton0 n t tmn0 n 00h 01h n 00h 01h n 00h 00h 01h 00h 01h clear clear clear count start interrupt acknowledgment interrupt acknowledgment interrupt acknowledgment interval time interval time remarks 1. interval time = (n + 1) t: n = 00h to ffh 2. n = 3, 4
chapter 6 8-bit timers 30 and 40 user?s manual u16995ej2v0ud 97 figure 6-9. timing of interval timer operati on with 8-bit resolution (when crn0 is set to 00h) count clock crn0 tcen0 inttmn0 ton0 00h tmn0 00h count start remark n = 3, 4 figure 6-10. timing of interval timer operati on with 8-bit resolution (when crn0 is set to ffh) count clock crn0 tcen0 inttmn0 ton0 ffh tmn0 ffh 00h 01h 00h 01h 00h 00h 00h 01h ffh ffh ffh clear clear clear count start remark n = 3, 4
chapter 6 8-bit timers 30 and 40 98 user?s manual u16995ej2v0ud figure 6-11. timing of interval ti mer operation with 8-bit resolution (when crn0 changes from n to m (n < m)) count clock crn0 tcen0 inttmn0 ton0 tmn0 n 00h 00h n 00h 01h 00h 01h m nm n m clear clear clear count start interrupt acknowledgment interrupt acknowledgment crn0 overwritten remark n = 3, 4 figure 6-12. timing of interval ti mer operation with 8-bit resolution (when crn0 changes from n to m (n > m)) count clock crn0 tcen0 inttmn0 ton0 tmn0 00h 00h 00h n ? 1 n mn m n m 00h ffh m h clear clear clear tmn0 overflows because m < n crn0 overwritten remark n = 3, 4
chapter 6 8-bit timers 30 and 40 user?s manual u16995ej2v0ud 99 figure 6-13. timing of interval ti mer operation with 8-bit resolution (when timer 40 match signal is sel ected for timer 30 count clock) timer 40 count clock cr40 tce40 inttm40 to40 tm40 n 00h m 00h 00h 01h m n m 00h m 00h 00h 01h y ? 1 y 00h y 00h y input clock to timer 30 (timer 40 match signal) to30 inttm30 tce30 cr30 tm30 clear clear clear clear count start count start remark n = 3, 4
chapter 6 8-bit timers 30 and 40 100 user?s manual u16995ej2v0ud (2) operation as square-wave output wit h 8-bit resolution (timer 40 only) square waves of any frequency can be output at an interval specified by t he value preset in 8-bit compare register 40 (cr40). to operate timer 40 for square-wave output, se ttings must be made in the following sequence. <1> set p60 to output mode (pm60 = 0). <2> set the output latch of p60 to 0. <3> disable operation of timer c ounter 40 (tm40) (tce40 = 0). <4> set a count clock for timer 40 and enable output of to40 (toe40 = 1). <5> set a count value in cr40. <6> enable the operation of tm40 (tce40 = 1). when the count value of tm40 matches the value set in cr40, the to40 pin output will be inverted. through application of this mechanism, square waves of any frequency can be output. as soon as a match occurs, tm40 is cleared to 00h and continues counting. at the same time, an in terrupt request signal (inttm40) is generated. the square-wave output is cleared to 0 by setting tce40 to 0. table 6-5 shows the square-wave output range, and figure 6-14 shows t he timing of square-wave output. caution be sure to stop the timer operation before overwriting the count cl ock with different data. table 6-5. square-wave output range of timer 40 (at f x = 5.0 mhz operation) tcl402 tcl401 tcl400 minimum pulse width maximum pulse width resolution 0 0 0 1/f x (0.2 s) 2 8 /f x (51 s) 1/f x (0.2 s) 0 0 1 2 2 /f x (0.8 s) 2 10 /f x (205 s) 2 2 /f x (0.8 s) 0 1 0 2/f x (0.4 s) 2 9 /f x (102 s) 2/f x (0.4 s) 0 1 1 2 2 /f x (0.8 s) 2 10 /f x (205 s) 2 2 /f x (0.8 s) 1 0 0 2 3 /f x (1.6 s) 2 11 /f x (410 s) 2 3 /f x (1.6 s) 1 0 1 2 4 /f x (3.2 s) 2 12 /f x (819 s) 2 4 /f x (3.2 s) remark f x : main system clock oscillation frequency
chapter 6 8-bit timers 30 and 40 user?s manual u16995ej2v0ud 101 figure 6-14. timing of square-wave output with 8-bit resolution count clock cr40 tce40 inttm40 to40 note n tm40 n 00h 01h n 00h 01h n 00h 01h 00h 01h clear clear clear count start interrupt acknowledgment interrupt acknowledgment interrupt acknowldgement square-wave output cycle t note the initial value of to40 is low level when output is enabled (toe40 = 1). remark square-wave output cycle = 2 (n + 1) t: n = 00h to ffh
chapter 6 8-bit timers 30 and 40 102 user?s manual u16995ej2v0ud 6.4.2 operation as 16-bit timer counter timers 30 and 40 can be used as 16-bit timer counters via a cascade connection. in this case, 8-bit timer counter 30 (tm30) is the higher 8 bits and 8-bit timer counter 40 (tm40) is the lower 8 bits. 8-bit timer 40 controls reset and clear. the following modes can be used for the 16-bit timer counter. ? interval timer with 16-bit resolution ? square-wave output with 16-bit resolution (1) operation as interval timer with 16-bit resolution the interval timer with 16-bit resolution repeatedly generates an interrupt at a time interval specified by the count value preset in 8-bit compare register 30 (cr30) and 8-bit compare register 40 (cr40). to operate as an interval timer with 16-bit resoluti on, settings must be made in the following sequence. <1> disable operation of 8-bit timer counter 30 (tm 30) and 8-bit timer counter 40 (tm40) (tce30 = 0, tce40 = 0). <2> disable timer output of to40 (toe40 = 0). <3> set the count clock for timer 40 (see table 6-4 ). <4> set the operation mode of timer 30 and ti mer 40 to 16-bit timer counter mode (see figures 6-4 and 6- 5 ). <5> set a count value in cr30 and cr40. <6> enable the operation of tm30 and tm40 (tce40 = 1 note ). note start and clear of the timer in the 16-bit timer counter mode are controlled by tce40 (the value of tce30 is invalid). when the count values of tm30 and tm40 match the values set in cr30 and cr40 respectively, both tm30 and tm40 are simultaneously cleared to 00h and counting continues. at the same time, an interrupt request signal (inttm40) is generated (i nttm30 is not generated). table 6-6 shows interval time, and figure 6-15 show s the timing of the interval timer operation. caution be sure to stop the timer operation before overwriting the count cl ock with different data. table 6-6. interval time with 16-bit resolution (at f x = 5.0 mhz operation) tcl402 tcl401 tcl400 minimum interval time maximum interval time resolution 0 0 0 1/f x (0.2 s) 2 16 /f x (13.1 ms) 1/f x (0.2 s) 0 0 1 2 2 /f x (0.8 s) 2 18 /f x (52.4 ms) 2 2 /f x (0.8 s) 0 1 0 2/f x (0.4 s) 2 17 /f x (26.2 ms) 2/f x (0.4 s) 0 1 1 2 2 /f x (0.8 s) 2 18 /f x (52.4 ms) 2 2 /f x (0.8 s) 1 0 0 2 3 /f x (1.6 s) 2 19 /f x (105 ms) 2 3 /f x (1.6 s) 1 0 1 2 4 /f x (3.2 s) 2 20 /f x (210 ms) 2 4 /f x (3.2 s) remark f x : main system clock oscillation frequency
chapter 6 8-bit timers 30 and 40 user?s manual u16995ej2v0ud 103 figure 6-15. timing of interval ti mer operation with 16-bit resolution interval time tm40 count clock tm40 count value cr40 tce40 inttm40 to40 ffh 00h 7fh 00h n 00h nn n n 80h 7fh 80h ffh 00h n 00h n n n tm30 count clock tm30 00h x x ? 1 01h cr30 x x x 7fh 80h ffh 00h n 00h n n n x x ? 1 00h t not cleared because tm30 does not match cleared because tm30 and tm40 match simultaneously count start interrupt not generated because tm30 does not match interrupt acknowledgment interrupt acknowledgment remark interval time = (256x + n + 1) t: x = 00h to ffh, n = 00h to ffh
chapter 6 8-bit timers 30 and 40 104 user?s manual u16995ej2v0ud (2) operation as square-wave output with 16-bit resolution square waves of any frequency can be out put at an interval specified by the count value preset in cr30 and cr40. to operate as a square-wave output with 16-bit resolution, settings must be made in the following sequence. <1> disable operation of tm30 and tm40 (tce30 = 0, tce40 = 0). <2> disable output of to40 (toe40 = 0). <3> set a count clock for timer 40. <4> set p60 to output mode (pm60 = 0) and p60 out put latch to 0 and enable to40 output (toe40 = 1). <5> set count values in cr30 and cr40. <6> enable the operati on of tm40 (tce40 = 1 note ). note start and clear of the timer in the 16-bit timer counter mode are controlled by tce40 (the value of tce30 is invalid). when the count values of tm30 and tm40 simult aneously match the values set in cr30 and cr40 respectively, the to40 pin output will be inverted. through application of this mechanism, square waves of any frequency can be output. as soon as a match o ccurs, tm30 and tm40 are cleared to 00h and counting continues. at the same time, an interrupt request si gnal (inttm40) is generated (inttm30 is not generated). the square-wave output is cleared to 0 by setting tce40 to 0. table 6-7 shows the square wave -output range, and figure 6-16 show s timing of square-wave output. caution be sure to stop the timer operation before overwriting the count cl ock with different data. table 6-7. square-wave output range with 16-bit resolution (at f x = 5.0 mhz operation) tcl402 tcl401 tcl400 minimum pulse width maximum pulse width resolution 0 0 0 1/f x (0.2 s) 2 16 /f x (13.1 ms) 1/f x (0.2 s) 0 0 1 2 2 /f x (0.8 s) 2 18 /f x (52.4 ms) 2 2 /f x (0.8 s) 0 1 0 2/f x (0.4 s) 2 17 /f x (26.2 ms) 2/f x (0.4 s) 0 1 1 2 2 /f x (0.8 s) 2 18 /f x (52.4 ms) 2 2 /f x (0.8 s) 1 0 0 2 3 /f x (1.6 s) 2 19 /f x (105 ms) 2 3 /f x (1.6 s) 1 0 1 2 4 /f x (3.2 s) 2 20 /f x (210 ms) 2 4 /f x (3.2 s) remark f x : main system clock oscillation frequency
chapter 6 8-bit timers 30 and 40 user?s manual u16995ej2v0ud 105 figure 6-16. timing of square-wave output with 16-bit resolution tm40 count clock tm40 count clock cr40 tce40 inttm40 to40 note ffh 00h 7fh 00h n 00h nn n n 80h 7fh 80h ffh 00h n 00h n n n tm30 count clock tm30 00h x x ? 1 01h cr30 x x x 7fh 80h ffh 00h n 00h n n n x x ? 1 00h not cleared because tm30 does not match cleared because tm30 and tm40 match simultaneously count start interrupt not generated because tm30 does not match interrupt acknowledgment interrupt acknowledgment square-wave output cycle/2 t note the initial value of to40 is low level when output is enabled (toe40 = 1). remark square-wave output cycle = 2 (256x + n + 1) t: x = 00h to ffh, n = 00h to ffh
chapter 6 8-bit timers 30 and 40 106 user?s manual u16995ej2v0ud 6.4.3 operation as carrier generator an arbitrary carrier clock generated by tm 40 can be output in the cycle set in tm30. to operate timers 30 and 40 as carrier generators, settings must be made in the following sequence. <1> disable operation of tm30 and tm40 (tce30 = 0, tce40 = 0). <2> disable timer output of to40 (toe40 = 0). <3> set count values in cr30, cr40, and crh40. <4> set the operation mode of timer 30 and timer 40 to carrier generator mode (see figures 6-4 and 6-5 ). <5> set the count clock for timer 30 and timer 40. <6> set remote control output to carrier pulse (rmc40 (bit 2 of carrier generator output control register 40 (tca40)) = 0). input the required value to nrzb 40 (bit 1 of tca40) by program. input a value to nrz40 (bit 0 of tca 40) before it is reloaded from nrzb40. <7> set p60 to output mode (pm60 = 0) and the p60 output latch to 0 and enable to40 output by setting toe40 to 1. <8> enable the operation of tm30 and tm40 (tce30 = 1, tce40 = 1). <9> save the nrzb40 value to a general-purpose register. <10> when inttm30 rises, the nrzb40 value is transferred to nrz40. after that, rewrite tca40 using an 8-bit memory manipulation instruction. input the value to be transferred nex t to nrz40 to nrzb40, and input the value saved in step <9> to nrz40. <11> generate the desired carrier si gnal by repeating steps <9> and <10>. the operation of the carrier generator is as follows. <1> when the count the value of tm40 matches the value set in cr40, an in terrupt request signal (inttm40) is generated and the output of time r 40 is inverted, which makes the com pare register switch from cr40 to crh40. <2> after that, when the count the value of tm40 matc hes the value set in crh40, an interrupt request signal (inttm40) is generated and t he output of timer 40 is inverted again, which makes the compare register switch from crh40 to cr40. <3> the carrier clock is generated by repeating <1> and <2> above. <4> when the count value of tm30 ma tches the value set in cr30, an in terrupt request signal (inttm30) is generated. the rising edge of inttm30 is the data reload signal of nrz b40 and is transferred to nrz40. <5> when nrz40 is 1, a carrier cl ock is output from to40 pin. cautions 1. tca40 cannot be set with a 1-bit memory manipulation instruction. be sure to use an 8-bit memory manipulation instruction. 2. the nrz40 flag can be rewritten only when the carrier generator output is stopped (toe40 = 0). the data of the flag is not changed even if a write instruction is executed while toe40 = 1. 3. when the carrier generator is stopped on ce and then started again, nrzb40 does not hold the previous data. re-set data to nrzb40. at this time, a 1-bit memory manipulation instruction must not be used. be sure to u se an 8-bit memory manipulation instruction. 4. to enable operation in the carrier genera tor mode, set a value to the compare registers (cr30, cr40, and crh40), and input the necessar y value to the nrzb 40 and nrz40 flags in advance. otherwise, the signa l of the timer match circui t will become unstable and the nrz40 flag will be undefined.
chapter 6 8-bit timers 30 and 40 user?s manual u16995ej2v0ud 107 figures 6-17 to 6-19 show the operat ion timing of the carrier generator. figure 6-17. timing of carrier generato r operation (when cr40 = n, crh40 = m (m > n)) tm40 count clock tm40 count value cr40 tce40 inttm40 m 00h n 00h 01h n crh40 m n 00h carrier clock n 00h 00h n m 00h 01h x 00h 01h x 00h 01h x 00h x 00h 01h tm30 cr30 tce30 inttm30 tm30 count clock 0 1 0 10 0 1 01 0 nrzb40 nrz40 to40 carrier clock clear clear clear clear count start x
chapter 6 8-bit timers 30 and 40 108 user?s manual u16995ej2v0ud figure 6-18. timing of carrier generato r operation (when cr40 = n, crh40 = m (m < n)) tm40 count clock tm40 count value cr40 tce40 inttm40 n 00h n crh40 m carrier clock n 00h 00h 01h x 00h 01h x 00h 01h x 00h x 00h 01h tm30 cr30 tce30 inttm30 tm30 count clock 0 1 0 10 0 1 01 0 nrzb40 nrz40 to40 carrier clock m 00h m m 00h m 00h clear clear clear clear count start x remark this figure shows an example of when the nrz40 value is changed while the carrier clock is high level.
chapter 6 8-bit timers 30 and 40 user?s manual u16995ej2v0ud 109 figure 6-19. timing of carrier genera tor operation (when cr40 = crh40 = n) tm40 count clock tm40 count value cr40 tce40 inttm40 n 00h 00h 00h n crh40 n n carrier clock 00h 00h n n 00h 01h x x 00h 01h x 00h 01h x 00h x 00h 01h tm30 cr30 tce30 inttm30 tm30 count clock 0 1 0 10 0 1 01 0 nrzb40 nrz40 to40 carrier clock n n 00h clear clear clear clear clear count start
chapter 6 8-bit timers 30 and 40 110 user?s manual u16995ej2v0ud 6.4.4 operation as pwm output (timer 40 only) in the pwm output mode, a pulse of any duty ratio can be output by setting a low-level width using cr40 and a high-level width using crh40. to operate timer 40 in pwm output mode, setti ngs must be made in the following sequence. <1> disable operation of tm40 (tce40 = 0). <2> disable timer output of to40 (toe40 = 0). <3> set count values in cr40 and crh40. <4> set the operation mode of time r 40 to carrier generator mode (see figure 6-5 ). <5> set the count clock for timer 40. <6> set p60 to output mode (pm60 = 0) and the p60 out put latch to 0 and enable time r output of to40 (toe40 = 1). <7> enable the operation of tm40 (tce40 = 1). the operation in the pwm out put mode is as follows. <1> when the count value of tm40 ma tches the value set in cr40, an in terrupt request signal (inttm40) is generated and the output of time r 40 is inverted, which makes the com pare register switch from cr40 to crh40. <2> a match between tm40 and cr40 clears the tm40 value to 00h and then counting starts again. <3> after that, when the count value of tm40 matches the value set in crh40, an interrupt request signal (inttm40) is generated and t he output of timer 40 is inverted again, which makes the compare register switch from crh40 to cr40. <4> a match between tm40 and crh40 clears the tm40 va lue to 00h and then counting starts again. a pulse of any duty ratio is output by repeating <1> to <4> above. fi gures 6-20 and 6-21 s how the operation timing in the pwm output mode.
chapter 6 8-bit timers 30 and 40 user?s manual u16995ej2v0ud 111 figure 6-20. pwm output mode timing (basic operation) tm40 count clock tm40 count value cr40 tce40 inttm40 00h n 00h 01h n crh40 m n to40 note 00h 00h 01h m 01h 01h m 00h clear clear clear clear count start note the initial value of to40 is low level when output is enabled (toe40 = 1). figure 6-21. pwm output mode timing (when cr40 and crh40 are overwritten) tm40 count clock tm40 count value cr40 tce40 inttm40 00h n 00h 01h n crh40 m n to40 note m x y 00h 00h x 00h x ym clear clear clear clear count start note the initial value of to40 is low level when output is enabled (toe40 = 1).
chapter 6 8-bit timers 30 and 40 112 user?s manual u16995ej2v0ud 6.5 notes on using 8-bit timers 30 and 40 (1) error on starting timer an error of up to 1.5 clocks is included in the time between when the timer is st arted and a match signal is generated. this is because the counter may be increment ed by detecting a rising edge at the timing at which the timer starts while the count clock is high level (see figure 6-22 ). figure 6-22. case in which erro r of 1.5 clocks (max.) occurs tcen0 tcen0 00h 01h 02h 03h if delay a > delay b when the timer starts while the selected clock is high level, an error of 1.5 clocks (max.) occurs. tmn0 count value count pulse clear signal selected clock clear signal 8-bit timer counter n0 (tmn0) count pulse delay a delay a delay b delay b selected clock remark n = 3, 4
user?s manual u16995ej2v0ud 113 chapter 7 watch timer 7.1 watch timer functions the watch timer has the following functions. watch timer interval timer the watch and interval timers can be used at the same time. figure 7-1 shows a block diagram of the watch timer. figure 7-1. block diagram of watch timer f x /2 7 f xt f w f w 2 4 f w 2 5 f w 2 6 f w 2 7 f w 2 8 f w 2 9 clear 9-bit prescaler selector clear 5-bit counter intwt intwti wtm7 wtm6 wtm5 wtm4 wtm1 wtm0 watch timer mode control register (wtm) internal bus selector
chapter 7 watch timer 114 user?s manual u16995ej2v0ud (1) watch timer the 4.19 mhz main system clock or 32.768 khz subsyst em clock is used to generate an interrupt request (intwt) at 0.5-second intervals. caution when the main system clo ck is operating at 5.0 mhz, it ca nnot be used to generate a 0.5- second interval. in this case, the subsystem clock, which operates at 32.768 khz, should be used instead. (2) interval timer the interval timer is used to generate an interr upt request (intwt) at specified intervals. table 7-1. interval time of interval timer interval at f x = 5.0 mhz operation at f x = 4.19 mhz operation at f xt = 32.768 khz operation 2 4 1/f w 409.6 s 488 s 488 s 2 5 1/f w 819.2 s 977 s 977 s 2 6 1/f w 1.64 ms 1.95 ms 1.95 ms 2 7 1/f w 3.28 ms 3.91 ms 3.91 ms 2 8 1/f w 6.55 ms 7.81 ms 7.81 ms 2 9 1/f w 13.1 ms 15.6 ms 15.6 ms remarks 1. f w : watch timer clock frequency (f x /2 7 or f xt ) 2. f x : main system clock oscillation frequency 3. f xt : subsystem clock oscillation frequency 7.2 watch timer configuration the watch timer includes the following hardware. table 7-2. configuration of watch timer item configuration counter 5 bits 1 prescaler 9 bits 1 control register watch timer mode control register (wtm)
chapter 7 watch timer user?s manual u16995ej2v0ud 115 7.3 register controlling watch timer the watch timer mode control register (wt m) is used to control the watch timer. watch timer mode control register (wtm) wtm selects a count clock for the watch timer and specif ies whether to enable clocking of the timer. it also specifies the prescaler interval and how the 5-bit counter is controlled. this register is set with a 1-bit or 8-bit memory manipulation instruction. reset input clears wtm to 00h. figure 7-2. format of watch timer mode control register symbol 7 6 5 4 3 2 <1> <0> address after reset r/w wtm wtm7 wtm6 wtm5 wtm4 0 0 wtm1 wtm0 ff4ah 00h r/w wtm7 watch timer count clock (f w ) selection 0 f x /2 7 (39.1 khz) 1 f xt (32.768 khz) wtm6 wtm5 wtm4 prescaler interval selection 0 0 0 2 4 /f w 0 0 1 2 5 /f w 0 1 0 2 6 /f w 0 1 1 2 7 /f w 1 0 0 2 8 /f w 1 0 1 2 9 /f w other than above setting prohibited wtm1 control of 5-bit counter operation 0 cleared after stop 1 started wtm0 watch timer operation 0 operation stopped (both prescaler and timer cleared) 1 operation enabled caution bits 2 and 3 must be set to 0. remarks 1. f w : watch timer clock frequency (f x /2 7 or f xt ) 2. f x : main system clock oscillation frequency 3. f xt : subsystem clock oscillation frequency 4. the parenthesized values apply to operation at f x = 5.0 mhz or f xt = 32.768 khz.
chapter 7 watch timer 116 user?s manual u16995ej2v0ud 7.4 watch timer operation 7.4.1 operation as watch timer the main system clock (4.19 mhz) or subsystem clock (32.768 khz) is used as a watch timer which generates 0.5-second intervals. the watch timer is used to generate an inte rrupt request at specified intervals. by setting bits 0 and 1 (wtm0 and wtm1) of the watch time r mode control register (wtm) to 1, the watch timer starts counting. by setting them to 0, the 5-bit counter is cleared and the watc h timer stops counting. when the interval timer also operates at the same time , only the watch timer can be started from 0 seconds by setting wtm1 to 0. however, an error of up to 2 9 1/f w seconds may occur for the first overflow of the watch timer (intwt) after a 0-second start because the 9-bi t prescaler is not cleared in this case. 7.4.2 operation as interval timer the interval timer is used to repeatedly generate an interrupt request at the interval s pecified by a preset count value. the interval time can be selected by bits 4 to 6 (wtm4 to wtm6) of the watch timer m ode control register (wtm). table 7-3. interval time of interval timer interval at f x = 5.0 mhz operation at f x = 4.19 mhz operation at f xt = 32.768 khz operation 2 4 1/f w 409.6 s 488 s 488 s 2 5 1/f w 819.2 s 977 s 977 s 2 6 1/f w 1.64 ms 1.95 ms 1.95 ms 2 7 1/f w 3.28 ms 3.91 ms 3.91 ms 2 8 1/f w 6.55 ms 7.81 ms 7.81 ms 2 9 1/f w 13.1 ms 15.6 ms 15.6 ms remarks 1. f w : watch timer clock frequency (f x /2 7 or f xt ) 2. f x : main system clock oscillation frequency 3. f xt : subsystem clock oscillation frequency
chapter 7 watch timer user?s manual u16995ej2v0ud 117 figure 7-3. watch timer/inte rval timer operation timing 0h start overflow overflow 5-bit counter count clock f w /2 9 watch timer interrupt intwt interval timer interrupt intwti watch timer interrupt time (0.5 s) watch timer interrupt time (0.5 s) interval timer (t) t caution when operation of the watc h timer and 5-bit counter has b een enabled by setting the watch timer mode control register (wt m) (setting wtm0 (bit 0 of wtm) to 1), the time until the first interrupt request after this se tting will not be exactly the same as th e watch timer interrupt time (0.5 s). this is because the 5-bit counter starts counting one cycle after the output of the 9-bit prescaler. the intwt signal will be generated at the set time from its second generation. remarks 1. f w : watch timer clock frequency 2. the parenthesized values apply to operation at f w = 32.768 khz.
118 user?s manual u16995ej2v0ud chapter 8 watchdog timer 8.1 watchdog timer functions the watchdog timer has the following functions. ? watchdog timer ? interval timer caution select the watchdog timer mode or interval timer mode by using the watchdog timer mode register (wdtm). (1) watchdog timer the watchdog timer is used to detect inadvertent program loop. when the inadvertent program loop is detected, a non-maskable interrupt or the reset signal can be generated. table 8-1. inadvertent program loop detection time of watchdog timer inadvertent program loop detection time at f x = 5.0 mhz operation 2 11 1/f x 410 s 2 13 1/f x 1.64 ms 2 15 1/f x 6.55 ms 2 17 1/f x 26.2 ms remark f x : main system clock oscillation frequency (2) interval timer the interval timer generates an inte rrupt at any preset intervals. table 8-2. interval time of watchdog timer interval time at f x = 5.0 mhz operation 2 11 1/f x 410 s 2 13 1/f x 1.64 ms 2 15 1/f x 6.55 ms 2 17 1/f x 26.2 ms remark f x : main system clock oscillation frequency
chapter 8 watchdog timer user?s manual u16995ej2v0ud 119 8.2 watchdog timer configuration the watchdog timer includes the following hardware. table 8-3. configuration of watchdog timer item configuration control registers watchdog timer clo ck selection register (tcl2) watchdog timer mode register (wdtm) figure 8-1. block diagram of watchdog timer internal bus internal bus prescaler selector controller f x 2 6 f x 2 8 f x 2 10 2 7-bit counter clear wdtif wdtmk tcl22 tcl21 watchdog timer clock selection register (tcl2) watchdog timer mode register (wdtm) wdtm4 run wdtm3 intwdt maskable interrupt request reset intwdt non-maskable interrupt request f x 2 4
chapter 8 watchdog timer 120 user?s manual u16995ej2v0ud 8.3 registers controlling watchdog timer the watchdog timer is controlled by the following two registers. ? watchdog timer clock selection register (tcl2) ? watchdog timer mode register (wdtm) (1) watchdog timer clock selection register (tcl2) tcl2 sets the watchdog timer count clock. this register is set with an 8-bit memory manipulation instruction. reset input clears tcl2 to 00h. figure 8-2. format of watchdog ti mer clock selection register symbol 7 6 5 4 3 2 1 0 address after reset r/w tcl2 0 0 0 0 0 tcl22 tcl21 0 ff42h 00h r/w tcl22 tcl21 watchdog timer count clock selection i nadvertent program loop detection or interval time 0 0 f x /2 4 (313 khz) 2 11 /f x (410 s) 0 1 f x /2 6 (78.1 khz) 2 13 /f x (1.64 ms) 1 0 f x /2 8 (19.5 khz) 2 15 /f x (6.55 ms) 1 1 f x /2 10 (4.88 khz) 2 17 /f x (26.2 ms) caution bits 0, 3 to 7 must be set to 0. remarks 1. f x : main system clock oscillation frequency 2. the parenthesized values apply to operation at f x = 5.0 mhz.
chapter 8 watchdog timer user?s manual u16995ej2v0ud 121 (2) watchdog timer mode register (wdtm) wdtm sets an operation mode of the watchdog timer, and enables/disables counting of the watchdog timer. this register is set with a 1-bit or 8-bit memory manipulation instruction. reset input clears wdtm to 00h. figure 8-3. format of watc hdog timer mode register symbol <7> 6 5 4 3 2 1 0 address after reset r/w wdtm run 0 0 wdtm4 wdtm3 0 0 0 fff9h 00h r/w run selection of operation of watchdog timer note 1 0 stops counting 1 clears counter and starts counting wdtm4 wdtm3 selection of operation mode of watchdog timer note 2 0 0 operation stopped 0 1 interval timer mode (when overflow occurs, a maskable interrupt occur) note 3 1 0 watchdog timer mode 1 (when overflow occurs, a non-maskable interrupt occurs) 1 1 watchdog timer mode 2 (when overflow occurs, reset operation starts) notes 1. once run has been set (1), it cannot be cleared (0 ) by software. theref ore, when counting is started, it cannot be stopped by any means other than reset input. 2. once wdtm3 and wdtm4 have been set (1), they cannot be cleared (0) by software. 3. the watchdog timer starts operations as an interval timer when run is set to 1. cautions 1. when the watchdog timer is cleared by setting run to 1, the actual overflow time is up to 0.8% shorter than the time set by the watchdog timer clock selection register (tcl2). 2. in watchdog timer mode 1 or 2, set wdtm4 to 1 after confirming that the wdtif (bit 0 of interrupt request flag register 0 (if0)) is set to 0. while wdtif is 1, a non-maskable interrupt is generate d upon write completion if watchdog ti mer mode 1 or 2 is selected.
chapter 8 watchdog timer 122 user?s manual u16995ej2v0ud 8.4 watchdog timer operation 8.4.1 operation as watchdog timer the watchdog timer detects an inadver tent program loop when bit 4 (w dtm4) of the watchdog timer mode register (wdtm) is set to 1. the count clock (inadvertent program loop detection time interval) of t he watchdog timer can be selected by bits 1 and 2 (tcl21 and tcl22) of the watchdog timer clock selection regi ster (tcl2). by setting bit 7 (run) of wdtm to 1, the watchdog timer is started. set run to 1 within the set inadvert ent program loop detection time interval after the watchdog timer has been started. by setting run to 1, t he watchdog timer can be cleared and start counting. if run is not set to 1, and the inadvertent program loop detection time is exceeded, the system is reset or a non-maskable interrupt is generated by the val ue of bit 3 (wdtm3) of wdtm. the watchdog timer continues operation in the halt mode, but stops in the st op mode. therefore, set run to 1 before entering the stop mode to clear the watchdog timer, and then ex ecute the stop instruction. cautions 1. the actual inadvertent program loop detection time may be up to 0.8% shorter than the set time. 2. when the subsystem clock is selected as th e cpu clock, the watchdog timer stops counting. in this case, therefore, the watchdog time r stops operation even though the main system clock is oscillating. table 8-4. inadvertent program loop detection time of watchdog timer tcl22 tcl21 inadvertent program loop detection time at f x = 5.0 mhz operation 0 0 2 11 1/f x 410 s 0 1 2 13 1/f x 1.64 ms 1 0 2 15 1/f x 6.55 ms 1 1 2 17 1/f x 26.2 ms remark f x : main system clock oscillation frequency
chapter 8 watchdog timer user?s manual u16995ej2v0ud 123 8.4.2 operation as interval timer when bit 4 (wdtm4) and bit 3 (wdtm3) of the watchdog timer mode register (wdtm) are set to 0 and 1, respectively, the watchdog timer also operates as an interv al timer that repeatedly generat es an interrupt at time intervals specified by a preset count value. select a count clock (or interval time) by setting bits 1 and 2 (tcl21 and tcl22) of the watchdog timer clock selection register (tcl2). the watchdog timer starts operation as an interval timer when the run bit (bit 7 of wdtm) is set to 1. in the interval timer mode, the interrupt mask flag (w dtmk) is valid, and a maskable interrupt (intwdt) can be generated. the priority of intwdt is set as the highest of all the maskable interrupts. the interval timer continues operation in the halt mode, but st ops in the stop mode. therefore, set run to 1 before entering the stop mode to cl ear the interval timer, and then execute the stop instruction. cautions 1. once bit 4 (wdtm4) of wdtm is set to 1 (when the watchdog timer mode is selected), the interval timer mode is not set , unless the reset signal is input. 2. the interval time immediat ely after the setting by wdtm may be up to 0.8% shorter than the set time. table 8-5. interval time of watchdog timer tcl22 tcl21 interval time at f x = 5.0 mhz operation 0 0 2 11 1/f x 410 s 0 1 2 13 1/f x 1.64 ms 1 0 2 15 1/f x 6.55 ms 1 1 2 17 1/f x 26.2 ms remark f x : main system clock oscillation frequency
124 user?s manual u16995ej2v0ud chapter 9 serial interface 10 ( pd78f9328 only) caution serial interface 10 is not available for mask rom versions. do not access the registers used for serial interface 10 when using a mask rom version. 9.1 serial interface 10 functions serial interface 10 has the following two modes. ? operation stop mode ? 3-wire serial i/o mode (1) operation stop mode this mode is used when serial transfer is not carri ed out. it enables a reduction in power consumption. (2) 3-wire serial i/o mode (ms b/lsb-first switchable) in this mode, 8-bit data transfer is carried out-first with three lines, one for the serial clock (sck10) and two for serial data (si10 and so10). the 3-wire serial i/o mode supports simultaneous trans mit and receive operations, reducing data transfer processing time. it is possible to switch the start bit of 8-bit dat a to be transmitted between t he msb and the lsb, thus allowing connection to devices with either start bit. the 3-wire serial i/o mode is effective for connecting di splay controllers and peripheral i/o such as the 75xl series, 78k series, and 17k series, which have inte rnal conventional clocked serial interfaces.
chapter 9 serial interface 10 ( pd78f9328 only) user?s manual u16995ej2v0ud 125 9.2 serial interface 10 configuration serial interface 10 includes the following hardware. table 9-1. configuration of serial interface 10 item configuration register transmit/receive shift register 10 (sio10) control register serial operation mode register 10 (csim10) port mode register 2 (pm2) port 2 (p2) (1) transmit/receive shi ft register 10 (sio10) sio10 is an 8-bit register used for parallel- to-serial conversion and to perform serial data transmission/reception in synchronization with serial clocks. this register is set with an 8-bit memory manipulation instruction. reset input makes sio10 undefined.
chapter 9 serial interface 10 ( pd78f9328 only) 126 user?s manual u16995ej2v0ud si10/p22 csie10 tps101 tps100 dir10 csck10 pm20 sck10/p20 intcsi10 f/f tps101 tps100 f x /2 2 f x /2 3 internal bus serial operation mode register 10 (csim10) transmit/receive shift register 10 (sio10) serial clock counter interrupt request generator clock controller selector selector so10/p21 pm21 output latch (p21) output latch (p20) figure 9-1. block diagra m of serial interface 10
chapter 9 serial interface 10 ( pd78f9328 only) user?s manual u16995ej2v0ud 127 9.3 registers controlling serial interface 10 serial interface 10 is controlled by the following three registers. ? serial operation mode register 10 (csim10) ? port mode register 2 (pm2) ? port 2 (p2) (1) serial operation mode register 10 (csim10) csim10 is used to control serial interface 10 and set the serial clock and start bit. this register is set with a 1-bit or 8- bit memory manipulation instruction. reset input clears csim10 to 00h. figure 9-2. format of serial operation mode register 10 symbol <7> 6 5 4 3 2 1 0 address after reset r/w csim10 csie10 0 tps101 tps100 0 dir10 csck10 0 ff72h 00h r/w csie10 operation control in 3-wire serial i/o mode 0 operation stopped 1 operation enabled tps101 tps100 count clock selecti on when internal clock is selected 0 0 f x /2 2 (1.25 mhz) 0 1 f x /2 3 (625 khz) other than above setting prohibited dir10 start bit specification 0 msb 1 lsb csck10 sio10 clock selection 0 input clock to sck10 pin from external 1 internal clock selected by tps100, tps101 cautions 1. bits 0, 3, and 6 must be set to 0. 2. switch operation mode after stoppi ng the serial transmit/receive operation. remarks 1. f x : main system clock oscillation frequency 2. the parenthesized values apply to operation at f x = 5.0 mhz.
chapter 9 serial interface 10 ( pd78f9328 only) 128 user?s manual u16995ej2v0ud (2) port mode register 2 (pm2) this register is used to set the i/o mode of port 2 in 1-bit units. pm2 is set with a 1-bit or 8-bit memory manipulation instruction. reset input sets pm2 to ffh. figure 9-3. format of port mode register 2 symbol 7 6 5 4 3 2 1 0 address after reset r/w pm2 1 1 1 1 1 pm22 pm21 pm20 ff22h ffh r/w pm2n i/o mode of p2n pin (n = 0 to 2) 0 output mode (output buffer is on) 1 input mode (output buffer is off) caution bits 3 to 7 must be set to 1. table 9-2. settings of serial interface 10 operating mode (1) operation stop mode csim10 pm22 p22 pm21 p21 pm20 p20 start shift p22/si10 p21/so10 p20/sck10 csie10 dir10 csck10 bit clock pin function pin function pin function 0 note 1 note 1 note 1 note 1 note 1 note 1 ? ? p22 p21 p20 other than above setting prohibited (2) 3-wire serial i/o mode csim10 pm22 p22 pm21 p21 pm20 p20 start shift p22/si10 p21/so10 p20/sck10 csie10 dir10 csck10 bit clock pin function pin function pin function 1 0 0 1 note 2 note 2 0 1 1 msb external clock si10 note 2 so10 (cmos output) sck10 input 1 0 1 internal clock sck10 output 1 1 0 1 lsb external clock sck10 input 1 0 1 internal clock sck10 output other than above setting prohibited notes 1. can be used as port function. 2. if used only for transmission, can be used as p22 (cmos i/o). remark : don?t care
chapter 9 serial interface 10 ( pd78f9328 only) user?s manual u16995ej2v0ud 129 9.4 serial interface 10 operation serial interface 10 provides the following two types of modes. ? operation stop mode ? 3-wire serial i/o mode 9.4.1 operation stop mode in the operation stop mode, serial transfer is not execut ed, therefore enabling a reduction in the power consumption. the p20/sck10, p21/so10, and p22/si10 pins can be used as normal i/o ports. (1) register setting operation stop mode is set by serial operation mode register 10 (csim10). (a) serial operation mode register 10 (csim10) csim10 is set with a 1-bit or 8-bit memory manipulation instruction. reset input clears csim10 to 00h. symbol <7> 6 5 4 3 2 1 0 address after reset r/w csim10 csie10 0 tps101 tps100 0 dir10 csck10 0 ff72h 00h r/w csie10 operation control in 3-wire serial i/o mode 0 operation stopped 1 operation enabled caution bits 0, 3, and 6 must be set to 0.
chapter 9 serial interface 10 ( pd78f9328 only) 130 user?s manual u16995ej2v0ud 9.4.2 3-wire serial i/o mode the 3-wire serial i/o mode is useful fo r connection of peripheral i/o and display controllers, etc., which incorporate a conventional clocked serial interface, such as the 75xl series, 78k series, 17k series. communication is performed using three lines: a serial clock line (sck10), serial output line (so10), and serial input line (si10). (1) register setting 3-wire serial i/o mode settings are performed usi ng serial operation mode register 10 (csim10). (a) serial operation mode register 10 (csim10) csim10 is set with a 1-bit or 8-bit memory manipulation instruction. reset input clears csim10 to 00h. symbol <7> 6 5 4 3 2 1 0 address after reset r/w csim10 csie10 0 tps101 tps100 0 dir10 csck10 0 ff72h 00h r/w csie10 operation control in 3-wire serial i/o mode 0 operation stopped 1 operation enabled tps101 tps100 count clock selecti on when internal clock is selected 0 0 f x /2 2 (1.25 mhz) 0 1 f x /2 3 (625 khz) other than above setting prohibited dir10 start bit specification 0 msb 1 lsb csck10 sio10 clock selection 0 input clock to sck10 pin from external 1 internal clock selected by tps100, tps101 cautions 1. bits 0, 3, and 6 must be set to 0. 2. switch operation mode after stoppi ng the serial transmit/receive operation. remarks 1. f x : main system clock oscillation frequency 2. the parenthesized values apply to operation at f x = 5.0 mhz.
chapter 9 serial interface 10 ( pd78f9328 only) user?s manual u16995ej2v0ud 131 (2) communication operation in the 3-wire serial i/o mode, data transmission/rec eption is performed in 8-bit units. data is transmitted/received bit by bit in syn chronization with the serial clock. transmit shift register 10 (sio10) shift operations are performed in synchronization with the fall of the serial clock (sck10). transmit data is then held in the so10 latch and output from the so 10 pin. also, receive data input to the si10 pin is latched in the i nput bits of sio10 on the rise of sck10. at the end of an 8-bit transfer, t he operation of sio10 stops automatically, and the interrupt request signal (intcsi10) is generated. figure 9-4. 3-wire serial i/o mode timing 12345678 di7 di6 di5 di4 di3 di2 di1 di0 do7 do6 do5 do4 do3 do2 do1 do0 end of transfer transfer starts at the falling edge of sck10 sck10 si10 so10 intcsi10 cautions 1. when data is writte n to sio10 in the serial operation disabled status (csie10 = 0), the data cannot be tran smitted or received. 2. when data is written to sio10 in the serial operation disabled status (csie10 = 0) and then serial operation is enabled (csie10 = 1), the data cannot be transmitted or received. 3. once data has been written to sio10 wit h the external serial clock selected (csck10 = 0), overwriting the data does not update the contents of sio10. 4. when csim10 is operated during data transmission/reception, data cannot be transmitted or received normally. 5. when sio10 is operate d during data transmission/r eception, the data cannot be transmitted or received normally. (3) transfer start serial transfer is started by setting transfer data to the transmit shift register 10 (sio10) when the following two conditions are satisfied. ? bit 7 (csie10) of serial operat ion mode register 10 (csim10) = 1 ? internal serial clock is stopped or sck10 is a high level after 8-bit serial transfer. termination of 8-bit transfer stops the serial transfe r automatically and generates the interrupt request signal (intcsi10).
user?s manual u16995ej2v0ud 132 chapter 10 lcd controller/driver 10.1 lcd controller/driver functions the functions of the lcd controller/driver of the pd179327 subseries are as follows. (1) automatic output of segment and common signal s based on automatic display data memory read (2) two different display modes: static 1/4 duty (1/3 bias) (3) four different frame frequencies, selectable in each display mode (4) up to 24 segment signal outputs (s0 to s23) and four common signal outputs (com0 to com3) (5) operation with a subsystem clock table 10-1 lists the maximum number of pixels that can be displayed in each display mode. table 10-1. maximu m number of pixels bias mode number of time slices common signals used maximum number of pixels ? static com0 (com1 to com3) 24 (24 segments 1 common) note 1 1/3 4 com0 to com3 96 (24 segments 4 commons) note 2 notes 1. 3-digit lcd panel, each digit having an 8-segment configuration. 2. 12-digit lcd panel, each digit having a 2-segment configuration. 10.2 lcd controller/driver configuration the lcd controller/driver consis ts of the following hardware. table 10-2. configuration of lcd controller/driver item configuration display outputs segment signals: 24 common signals: 4 control registers lcd display mode register 0 (lcdm0) lcd clock control register 0 (lcdc0) port function register 8 (pf8)
chapter 10 lcd controller/driver user?s manual u16995ej2v0ud 133 figure 10-1. block diagram of lcd controller/driver lcdc03 lcdc02 lcdc01 lcdc00 2 2 f lcd 2 6 f lcd 2 7 f lcd 2 8 f lcd 2 9 lcdon0 vaon0 v lc0 v lc0 v lc0 com0 com1 com2 com3 3210 3210 65 74 fa00h lcdon0 3210 3210 65 74 fa16h lcdon0 s22/p80 f x /2 5 f x /2 6 f x /2 7 f xt s0 f lcd 1 3 2 3 v ss r lcd r lcd r lcd 3210 3210 654 fa17h lcdon0 s23 pf85 pf84 pf83 pf82 pf80 pf81 pf80 3210 3210 65 74 fa11h lcdon0 s17/p85 pf85 lcdcl lcdm02 7 internal bus prescaler lcd clock selector selector lcd clock control register 0 (lcdc0) lcd display mode register 0 (lcdm0) lcd drive voltage controller segment driver common driver display data memory selector segment driver timing controller selector segment driver port function register 8 (pf8) selector segment driver gate voltage amplifier level shifter level shifter level shifter level shifter selector
chapter 10 lcd controller/driver 134 user?s manual u16995ej2v0ud 10.3 registers controlling lcd controller/driver lcd display mode register 0 (lcdm0) lcd clock control register 0 (lcdc0) port function register 8 (pf8) (1) lcd display mode register 0 (lcdm0) lcdm0 specifies whether to enable di splay operation. it also specifie s the operation mode and display mode. this register is set with a 1-bit or 8-bit memory manipulation instruction. reset input clears lcdm0 to 00h.
chapter 10 lcd controller/driver user?s manual u16995ej2v0ud 135 figure 10-2. format of lcd display mode register 0 symbol <7> <6> 5 4 3 2 1 0 address after reset r/w lcdm0 lcdon0 vaon0 0 0 0 lcdm02 0 0 ffb0h 00h r/w lcdon0 lcd display enable/disable 0 display off (all segment outputs are unselected for signal output) 1 display on vaon0 lcd controller/driver operation mode note 1 0 no gate voltage amplification (for v lc0 = 2.7 to 5.5 v display) 1 gate voltage amplification enabled (for v lc0 = 1.8 to 5.5 v display) lcdm02 display mode selection note 2 0 four-time slot, 1/3 bias mode 1 static mode notes 1. when lcd display is not performed, the power c onsumption can be lowered by clearing vaon0 to 0. 2. to set the stop mode while the main system clo ck is selected as the lcd source clock, select the static mode (lcdm02 = 1). cautions 1. bits 0,1, 3 to 5 must be set to 0. 2. when operating vaon0, follo w the procedure described below. a. to stop gate voltage amplification afte r switching display status from on to off : 1) set to display off st atus by setting lcdon0 = 0. 2) stop gate voltage amplification by setting vaon0= 0. b. to stop gate voltage amplification during display on status: setting prohibited. be sure to stop gate voltage amplif ication after setting display off. c. to set display on from gate voltage amplification stop status: 1) start gate voltage amplification by setti ng vaon0 = 1, then wait for about 500 ms. 2) set display on by setting lcdon0 = 1. d. to start voltage amplification during display on status: setting prohibited. be sure to setting di splay off, and follow the procedure in c. 3. when the main system clo ck is selected as the lcd source cl ock, if the stop mode is selected, an abnormal display may occur. before selecti ng the stop mode, disable display and select the static mode (lcdon0 = 0 and lcdm02 = 1). if the subsystem clock is selected as th e lcd source clock, a normal opera tion is performed in the stop mode. 4. the lcd may momentarily light for 1 cycl e immediately after th e display has been turned on/off because the waveform has not become stabilized.
chapter 10 lcd controller/driver 136 user?s manual u16995ej2v0ud (2) lcd clock control register 0 (lcdc0) lcdc0 specifies the lcd source clock and lcd clock. the frame frequency is determined by the lcd clock and the number of time divisions. this register is set with a 1-bit or 8-bit memory manipulation instruction. reset input clears lcdc0 to 00h. figure 10-3. format of lcd clock control register 0 symbol 7 6 5 4 3 2 1 <0> address after reset r/w lcdc0 0 0 0 0 lcdc03 lcdc02 lcdc01 lcdc00 ffb2h 00h r/w lcdc03 lcdc02 lcd source clock (f lcd ) selection note 0 0 f xt (32.768 khz) 0 1 f x /2 5 (156.3 khz) 1 0 f x /2 6 (78.1 khz) 1 1 f x /2 7 (39.1 khz) lcdc01 lcdc00 lcd clock (lcdcl) selection 0 0 f lcd /2 6 0 1 f lcd /2 7 1 0 f lcd /2 8 1 1 f lcd /2 9 note specify an lcd source clock (f lcd ) frequency of at least 32 khz. remarks 1. f x : main system clock oscillation frequency 2. f xt : subsystem clock oscillation frequency 3. the parenthesized values apply to operation at f x = 5.0 mhz or f xt = 32.768 khz. cautions 1. bits 4 to 7 must be set to 0. 2. be sure to turn off the display (lcdon = 0) and stop the voltage amplifier (vaon0 = 0) before changing the lcdc0 settings. for example, table 10-3 lists the frame frequencies used when f xt (32.768 khz) is supplied to the lcd source clock (f lcd ). table 10-3. frame frequencies (hz) lcd clock (lcdcl) time division f xt /2 9 (64 hz) f xt /2 8 (128 hz) f xt /2 7 (256 hz) f xt /2 6 (512 hz) static 64 128 256 512 4 16 32 64 128
chapter 10 lcd controller/driver user?s manual u16995ej2v0ud 137 (3) port function register 8 (pf8) pf8 specifies whether s17/p85 to s22/p80 are used as lcd segment signal outputs or general-purpose ports in 1-bit units. this register is set with a 1-bit or 8-bit memory manipulation instruction. reset input clears pf8 to 00h. figure 10-4. format of port function register 8 symbol 7 6 5 4 3 2 1 0 address after reset r/w pf8 0 0 pf85 pf84 pf83 pf82 pf81 pf80 ff58h 00h r/w pf8n port function of p8n (n = 0 to 5) 0 operates as a general-purpose port 1 operates as an lcd segment signal output cautions 1. bits 6 and 7 must be set to 0. 2. when port 8 is used as a general-pur pose port, observe the following restriction (because an esd protection circui t for lcd pins (on the high-level side of port 8) is connected to v lc0 ). ? when any one of pins p80/s22 to p85/s 17 is used as a general-purpose input port pin, use the microcontroller at v dd = v lc0 or v dd < v lc0 . there is no restriction when all of pins p80/s22 to p85/s17 ar e used as lcd segment pins or general-purpo se output port pins. p8n/sm sm output signal p8n input signal v dd v ss pf8n v ss v lc0 rd p-ch pm8n v lc0 n-ch v ss p8n output signal segment buffer if a voltage higher than v lc0 is input to the p8n/sm pin, the current flows from the pin to v lc0 . as a result, the voltage of v lc0 becomes unstable.
chapter 10 lcd controller/driver 138 user?s manual u16995ej2v0ud remark sm: lcd segment output (m = 22 to 17) p8n: bit n of port 8 (n = 0 to 5) pf8n: bit n of port function register 8 (n = 0 to 5) rd: port 8 read signal 10.4 setting lcd controller/driver set the lcd controller/driver using the following procedure. <1> set the frame frequency using lcd clock control register 0 (lcdc0). <2> set vaon0 (bit 6 of lcdm0) (vaon0 = 1). wait for 500 ms or more after setting vaon0. <3> start output corresponding to each display data memory by setting lcdon0 (bit 7 of lcdm0) (lcdon0 =1). <1> set the frame frequency using lcd clock control register 0 (lcdc0). <2> start output corresponding to each display data memory by setting lcdon0 (bit 7 of lcdm0) (lcdon0 =1).
chapter 10 lcd controller/driver user?s manual u16995ej2v0ud 139 10.5 lcd display data memory the lcd display data memory is mapped at addresses fa00h to fa17h. data in the lcd display data memory can be displayed on the lcd panel us ing the lcd controller/driver. figure 10-5 shows the relationship between the c ontents of the lcd disp lay data memory and the segment/common outputs. that part of the display data memory which is not used for display can be used as ordinary ram. figure 10-5. relationship between lcd display data memory cont ents and segment/common outputs s23 fa17h s22 fa16h s21 fa15h s20 s2 fa02h s1 fa01h s0 fa00h com3 com2 com1 com0 b 7 b 6 b 5 b 4 b 3 b 2 b 1 b 0 address caution no memory has been installe d as the higher 4 bits of the lcd di splay data memory. be sure to set 0 to them.
chapter 10 lcd controller/driver 140 user?s manual u16995ej2v0ud 10.6 common and segment signals each pixel of the lcd panel turns on when the pot ential difference between the corresponding common and segment signals becomes higher than a s pecific voltage (lcd drive voltage, v lcd ). it turns off when the potential difference becomes lower than v lcd . applying dc voltage to the common and segment signals for an lcd panel would deteriorate it. to avoid this problem, this lcd panel is driven with ac voltage. (1) common signals each common signal is selected sequentially according to a specified number of time slots at the timing listed in table 10-4. table 10-4. com signals com signal number of time slots com0 com1 com2 com3 static display mode four-time slot mode (2) segment signals the segment signals correspond to 24 bytes of lcd display data memory (fa00h to fa17h). bits 0, 1, 2, and 3 of each byte are read in synchronization with com0, com1, com2, and com3, respectively. if the contents of each bit are 1, it is converted to the select vo ltage, and if 0, it is converted to the deselect voltage. the conversion results are output to the segment pins (s0 to s23). check, with the information given above, what combination of the front-s urface electrodes (corresponding to the segment signals) and the rear-sur face electrodes (corresponding to the common signals) forms display patterns in the lcd display data memory, and write t he bit data that corresponds to the desired display pattern on a one-to-one basis. lcd display data memory bits 1 to 3 are not used for lcd display in the static disp lay. so these bits can be used for purposes other than display. lcd display data memory bits 4 to 7 are fixed to 0. (3) output waveforms of common and segment signals the voltages listed in t able 10-5 are output as co mmon and segment signals. when both common and segment signals are at t he select voltage, a display on-voltage of v lcd is obtained. the other combinations of the signals correspond to the display off-voltage.
chapter 10 lcd controller/driver user?s manual u16995ej2v0ud 141 table 10-5. lcd drive voltage (a) static display mode select signal level deselect signal level segment signal common signal v ss0 /v lc0 v lc0 /v ss0 v lc0 /v ss0 ?v lcd /+v lcd 0 v/0 v (b) 1/3 bias method select signal level deselect signal level segment signal common signal v ss0 /v lc0 v lc1 /v lc2 select signal level v lc0 /v ss0 ?v lcd /+v lcd ? v lcd /+ v lcd deselect signal level v lc2 /v lc1 ? v lcd /+ v lcd ? v lcd /+ v lcd figure 10-6 shows the common signal waveforms, and figur e 10-7 shows the voltages and phases of the common and segment signals. figure 10-6. common signal waveforms (a) static display mode com0 (static display) t f = t v lc0 v ss v lcd t: one lcd clock period t f : frame frequency (b) 1/3 bias method t f = 4 t comn (four-time slot mode) v lc0 v lcd v lc1 v lc2 v ss t: one lcd clock period t f : frame frequency 1 3 1 3 1 3 1 3 1 3 1 3
chapter 10 lcd controller/driver 142 user?s manual u16995ej2v0ud figure 10-7. voltages and phases of common and segment signals (a) static display mode select deselect common signal segment signal v lc0 v ss v lcd v lc0 v ss v lcd tt t: one lcd clock period (b) 1/3 bias method select deselect common signal segment signal v lc0 v ss v lcd v lc0 v ss v lcd tt v lc2 v lc2 v lc1 v lc1 t: one lcd clock period
chapter 10 lcd controller/driver user?s manual u16995ej2v0ud 143 10.7 display modes 10.7.1 static display example figure 10-9 shows how the three-digit lcd panel having the display pattern shown in figure 10-8 is connected to the segment signals (s0 to s23) and the common signal (com0) of the pd179327 subseries chip. this example displays data "12.3" in the lcd panel. the contents of the di splay data memory (addresses fa00h to fa17h) correspond to this display. the following description focuses on numeral "2." ( ) disp layed in the second digit. to display "2." in the lcd panel, it is necessary to apply the select or deselect voltage to the s8 to s15 pins according to table 10-6 at the timing of the common signal com0; see figure 10-8 fo r the relationship between the segment signals and lcd segments. table 10-6. select and deselect voltages (com0) segment s8 s9 s10 s11 s12 s13 s14 s15 common com0 select deselect select select deselect select select select according to table 10-6, it is determi ned that the bit-0 pattern of the disp lay data memory locations (fa08h to fa0fh) must be 10110111. figure 10-10 shows the lcd drive waveforms of s11 and s 12, and com0. when the select voltage is applied to s11 at the timing of com0, an alternate rectangle waveform, +v lcd / ? v lcd , is generated to turn on the corresponding lcd segment. com1 to com3 are supplied with the same waveform as for com0. so, com0 to com3 may be connected together to increase t he driving capacity. figure 10-8. static lcd display pattern and electrode connections s 8n+3 s 8n+2 s 8n+5 s 8n+1 s 8n s 8n+4 s 8n+6 s 8n+7 com0 remark n = 0 to 2
chapter 10 lcd controller/driver 144 user?s manual u16995ej2v0ud figure 10-9. example of connecting static lcd panel 000001101110110110101110 bit 0 bit 2 bit 1 bit 3 timing strobe data memory address lcd panel fa00h 1 2 3 4 5 6 7 8 9 a b c d e f fa10h 1 2 3 4 5 6 7 s 0 s 1 s 2 s 3 s 4 s 5 s 6 s 7 s 8 s 9 s 10 s 11 s 12 s 13 s 14 s 15 s 16 s 17 s 18 s 19 s 20 s 21 s 22 s 23 com 3 com 2 com 1 com 0 can be connected together
chapter 10 lcd controller/driver user?s manual u16995ej2v0ud 145 figure 10-10. static l cd drive waveform examples t f v lc0 v ss com0 v lc0 v ss s11 v lc0 v ss s12 +v lcd 0 com0 to s12 ?v lcd +v lcd 0 com0 to s11 ?v lcd
chapter 10 lcd controller/driver 146 user?s manual u16995ej2v0ud 10.7.2 four-time slot display example figure 10-12 shows how the 12-digit lcd panel having the di splay pattern shown in figure 10-11 is connected to the segment signals (s0 to s23) and the common signals (com0 to com3) of the pd179327 subseries chip. this example displays data ?123456.789012? in the lcd panel. t he contents of the displa y data memory (addresses fa00h to fa17h) correspond to this display. the following description focuses on numeral ?6.? ( ) disp layed in the seventh digit. to display ?6.? in the lcd panel, it is necessary to apply the select or deselect volt age to the s12 and s13 pins acco rding to table 10-7 at the timing of the common signals com0 to com3; see figure 10-11 for the relationship bet ween the segment signals and lcd segments. table 10-7. select and desel ect voltages (com0 to com3) segment common s12 s13 com0 select select com1 deselect select com2 select select com3 select select according to table 10-7, it is dete rmined that the display data memory loca tion (fa0ch) that corresponds to s12 must contain 1101. figure 10-13 shows examples of lcd drive waveforms between the s12 signal and each common signal. when the select voltage is applied to s12 at the ti ming of com0, an alternate rectangle waveform, +v lcd /?v lcd , is generated to turn on the corresponding lcd segment. figure 10-11. four-time slot lcd displ ay pattern and electrode connections remark n = 0 to 11 com0 s 2n com1 s 2n+1 com2 com3
chapter 10 lcd controller/driver user?s manual u16995ej2v0ud 147 figure 10-12. example of connecting four-time slot lcd panel 000101101111111111110001 011111111010011111010111 011001010111011101110110 001010001011001000100010 bit 3 bit 2 bit 1 bit 0 timing strobe data memory address lcd panel fa00h 1 2 3 4 5 6 7 8 9 a b c d e f fa10h 1 2 3 4 5 6 7 s 0 s 1 s 2 s 3 s 4 s 5 s 6 s 7 s 8 s 9 s 10 s 11 s 12 s 13 s 14 s 15 s 16 s 17 s 18 s 19 s 20 s 21 s 22 s 23 com 3 com 2 com 1 com 0
chapter 10 lcd controller/driver 148 user?s manual u16995ej2v0ud figure 10-13. four-time slot lcd drive wavef orm examples t f v lc0 v lc2 com0 +v lcd 0 com0-s12 ? v lcd v lc1 +1/3v lcd ? 1/3v lcd v ss v lc0 v lc2 com1 v lc1 v ss v lc0 v lc2 com2 v lc1 v ss v lc0 v lc2 com3 v lc1 v ss +v lcd 0 com1-s12 ? v lcd +1/3v lcd ? 1/3v lcd v lc0 v lc2 s12 v lc1 v ss remark the waveforms of com2-s12 and com3 -s12 are not shown in the above chart.
user?s manual u16995ej2v0ud 149 chapter 11 power-on-clear circuits pd179327 subseries provides a power-on-clear (poc) circuit. in the flash memory version ( pd78f9328), the poc circuit is always operat ing. however, it can only be used when selected by a mask option in mask rom versions ( pd179322, 179322a, 179324, 179324a, 179326, and 179327) (see chapter 16 mask options ). 11.1 power-on-clear circuit functions the power-on-clear circuits include the following function. (1) power-on-clear (poc) circuit compares the detection voltage (v poc ) with the power supply voltage (v dd ) and generates an internal reset signal if v dd < v poc . this circuit can operate even in stop mode. 11.2 power-on-clear circuit configuration figure 11-1 shows the block diagram of the power-on-clear circuits. figure 11-1. block diagram of power-on-clear circuit pocof1 power-on-clear register 1 (pocf1) internal bus ? + detection voltage source (v poc ) v dd v dd internal reset signal
chapter 11 power-on-clear circuits user?s manual u16995ej2v0ud 150 11.3 register controlling power-on-clear circuit the power-on-clear circuits are c ontrolled by the following register. power-on-clear register 1 (pocf1) (1) power-on-clear register 1 (pocf1) pocf1 controls poc circuit operation. this register is set with a 1-bit or 8-bit memory manipulation instruction. figure 11-2. format of power-on-clear register 1 symbol 7 6 5 4 3 <2> 1 0 address after reset r/w pocf1 0 0 0 0 0 pocof1 0 0 ffddh 00h note r/w pocof1 poc output detection flag 0 non-generation of reset signal by poc or in cleared state due to a write operation to pocf1 1 generation of reset signal by poc note this value is 04h only after a power-on-clear reset. 11.4 power-on-clear circuit operation the poc circuit compares the detection voltage (v poc ) with the power supply voltage (v dd ) and generates an internal reset signal if v dd < v poc . when a reset is generated via the power-on-clear circuit in bit 2 (pocof1) on the power-on-clear register (pocf1) is set (1). this bit is then cleared (0) by an instru ction written to pocf1. after a power-on-clear reset (i.e. after program execution has started from address 0000h), a power failure can be detected by detecting pocof1. caution use of the poc circuit can be selected by a mask option in the case of the mask rom version. with the pd78f9328, use of the po c circuit cannot be selected (always operating). figure 11-3. timing of internal r eset signal generation of poc circuit power supply voltage (v dd ) detection voltage (v poc ) 1.8 v time internal reset signal
user?s manual u16995ej2v0ud 151 chapter 12 interrupt functions 12.1 interrupt function types the following two types of in terrupt functions are used. (1) non-maskable interrupt this interrupt is acknowledged unconditionally. it does not undergo interrupt priority control and is given top priority over all other interrupt requests. a standby release signal is generated. one interrupt source from the watchdog timer is incorporated as a non-maskable interrupt. (2) maskable interrupt this interrupt undergoes mask control. if two or more interrupts with the same priority are simultaneously generated, each interrupt has a predetermined priority as shown in table 12-1. a standby release signal is generated. 2 external and 5 (6 for the pd78f9328) internal interrupt sources ar e incorporated as maskable interrupts. 12.2 interrupt sources and configuration a total of 8 (9 for the pd78f9328) non-maskable and maskable interrupts are incorporated as interrupt sources (see table 12-1 ).
chapter 12 interrupt functions 152 user?s manual u16995ej2v0ud table 12-1. interrupt source list interrupt source interrupt type priority note 1 name trigger internal/ external vector table address basic configuration type note 2 non-maskable ? intwdt watchdog timer overflow (with watchdog timer mode 1 selected) (a) 0 intwdt watchdog timer overflow (with interval timer mode selected) internal 0004h (b) 1 intp0 pin input edge detection external 0006h (c) 2 intcsi10 end of serial interface 10 3-wire sio transfer reception note 3 0008h note 3 3 intwt watch timer interrupt 000ah 4 inttm30 generation of 8-bit timer 30 matching signal 000ch 5 inttm40 generation of 8-bit timer 40 matching signal internal 000eh (b) 6 intkr00 key return signal detection external 0010h (c) maskable 7 intwti watch timer interval timer interrupt internal 0012h (b) notes 1. priority is the priority order when more than one maskable interrupt request is generated at the same time. 0 is the highest priority and 7 is the lowest. 2. basic configuration types (a), (b), and (c) correspond to (a), (b), and (c) in figure 12-1. 3. the pd78f9328 only remark there are two interrupt sources for the wa tchdog timer (intwdt): non-maskable and maskable interrupts (internal). either one (but not both) should be selected for actual use.
chapter 12 interrupt functions user?s manual u16995ej2v0ud 153 figure 12-1. basic configuration of interrupt function (a) internal non-maskable interrupt internal bus interrupt request vector table address generator standby release signal (b) internal maskable interrupt mk if ie internal bus interrupt request vector table address generator standby release signal (c) external maskable interrupt mk if ie internal bus intm0, krm00 interrupt request edge detector vector table address generator standby release signal intp0: external interrupt mode register 0 krm00: key return mode register 00 if: interrupt request flag ie: interrupt enable flag mk: interrupt mask flag
chapter 12 interrupt functions 154 user?s manual u16995ej2v0ud 12.3 registers controlling interrupt function the following five types of registers are used to control the interrupt functions. ? interrupt request flag register 0 (if0) ? interrupt mask flag register 0 (mk0) ? external interrupt mode register 0 (intm0) ? program status word (psw) ? key return mode register 00 (krm00) table 12-2 gives a listing of interrupt request flag and interrupt mask flag names corresponding to interrupt requests. table 12-2. flags corresponding to interrupt request signal name interrupt request signal name interrupt request flag interrupt mask flag intwdt intp0 intcsi10 note intwt inttm30 inttm40 intkr00 intwti wdtif pif0 csiif10 note wtif tmif30 tmif40 krif00 wtiif wdtmk pmk0 csimk10 note wtmk tmmk30 tmmk40 krmk00 wtimk note the pd78f9328 only (1) interrupt request flag register 0 (if0) an interrupt request flag is set (1) when the co rresponding interrupt request is generated, or when an instruction is executed. it is cl eared (0) when the interrupt request is acknowledged, when the reset signal is input, or when an instruction is executed. if0 is set with a 1-bit or 8-bit memory manipulation instruction. reset input clears if0 to 00h. figure 12-2. format of interrupt request flag register 0 symbol <7> <6> <5> <4> <3> <2> <1> <0> address after reset r/w if0 wtiif krif00 tmif40 tmif30 wtif csiif10 note pif0 wdtif ffe0h 00h r/w if interrupt request flag 0 no interrupt request signal generated 1 an interrupt request signal is generated and an interrupt request made note provided in the pd78f9328 only. be sure to clear 0 for a mask rom version. cautions 1. the wdtif flag can be read/written only when the wa tchdog timer is being used as an interval timer. it must be cleared to 0 if the watchdog ti mer is used in watchdog timer mode 1 or 2.
chapter 12 interrupt functions user?s manual u16995ej2v0ud 155 cautions 2. because p61 functions alternately as an external interr upt input, when the output level changes after the output mode of the port f unction is specified, the interrupt request flag will be inadvertently set. therefore, be sure to preset the interrupt mask flag (pmk0) to 1 before using the port in output mode. 3. when an interrupt is acknowledged, the in terrupt request flag is automatically cleared and then the interrupt routine is started. (2) interrupt mask flag register 0 (mk0) interrupt mask flags are used to enable and di sable the corresponding maskable interrupts. mk0 is set with a 1-bit or 8-bit memory manipulation instruction. reset input sets mk0 to ffh. figure 12-3. format of interrupt mask flag register 0 symbol <7> <6> <5> <4> <3> <2> <1> <0> address after reset r/w mk0 wtimk krmk00 tmmk40 tmmk30 wtmk csimk10 note pmk0 wdtmk ffe4h ffh r/w mk interrupt servicing control 0 interrupt servicing enabled 1 interrupt servicing disabled note provided in the pd78f9328 only. be sure to set 1 for a mask rom version. cautions 1. when the watchdog timer is being used in watchdog timer mode 1 or 2, any attempt to read the wdtmk flag results in an undefined value being detected. 2. because p61 functions alte rnately as an external interrupt input, when the output level changes after the output mode of the port f unction is specified, the interrupt request flag will be inadvertently set. therefore, be sure to preset the interrupt mask flag (pmk0) to 1 before usi ng the port in output mode.
chapter 12 interrupt functions 156 user?s manual u16995ej2v0ud (3) external interrupt m ode register 0 (intm0) intm0 is used to specify the valid edge for intp0. this register is set with a 1-bit or 8-bit memory manipulation instruction. reset input clears intm0 to 00h. figure 12-4. format of external interrupt mode register 0 symbol 7 6 5 4 3 2 1 0 address after reset r/w intm0 0 0 0 0 es01 es00 0 0 ffech 00h r/w es01 es00 intp0 valid edge selection 0 0 falling edge 0 1 rising edge 1 0 setting prohibited 1 1 both rising and falling edges cautions 1. bits 0, 1, and 4 to 7 must be set to 0. 2. before setting intm0, set (1) the interr upt mask flag (pmk0) to disable interrupts. to enable interrupts, clear (0) the interr upt request flag (pif0), then clear (0) the interrupt mask flag (pmk0). (4) program status word (psw) the program status word is a regist er used to hold the instruction execut ion result and the current status for interrupt requests. the ie flag to set maskable interrupt enable/disable is mapped. besides 8-bit unit read/write, this register can carry out operations wit h a bit manipulation instruction and dedicated instructions (ei, di). w hen a vectored interrupt is acknowledged, the psw is automatically saved into a stack, and the ie flag is reset to 0. reset input sets psw to 02h. figure 12-5. configuration of program status word ie z 0 ac 0 0 1 cy psw 76543210 ie 0 1 02h symbol after reset used when normal instruction is executed interrupt acknowledgement enabled/disabled disabled enabled
chapter 12 interrupt functions user?s manual u16995ej2v0ud 157 (5) key return mode register 00 (krm00) this register is used to specify whether the key re turn signal (falling edge of port 4) is to be detected. this register is set with a 1-bit or 8-bit memory manipulation instruction. reset input clears krm00 to 00h. figure 12-6. format of key return mode register 00 symbol 7 6 5 4 3 2 1 0 address after reset r/w krm00 0 0 0 0 0 0 0 krm00 fff5h 00h r/w krm00 key return signal detection control 0 no detection 1 detection (detecting falling edge of port 4) cautions 1. bits 1 to 7 must be set to 0. 2. before setting krm00, always set bit 6 of mk 0 (krmk00 = 1) to disable interrupts. after setting krm00, clear krmk00 after clearing bit 6 of if1 (krif00 = 0) to enable interrupts. 3. on-chip pull-up resistors are automatica lly connected in input mode to the pins specified for key retu rn signal detection (p40 to p43). although these resistors are disconnected when the mode changes to out put, key return signal detection continues unchanged. 4. the key return signal can be detected while all of p40 to p43 are high level. the key return signal cannot be detected while even one of p40 to p43 is low, even if any other key return pin goes low. figure 12-7. block diagram of falling edge detector p40/kr00 p41/kr01 p42/kr02 p43/kr03 falling edge detector krmk00 intkr00 standby release signal key return mode register 00 (krm00) note selector note selector that selects t he pin used for falling edge input
chapter 12 interrupt functions 158 user?s manual u16995ej2v0ud 12.4 interrupt servicing operation 12.4.1 non-maskable interrupt request acknowledgment operation the non-maskable interrupt request is unconditionally ack nowledged even when interrupts are disabled. it is not subject to interrupt priority control and takes precedence over all other interrupts. when the non-maskable interrupt request is acknowledged, psw and pc are saved to the stack in that order, the ie flag is reset to 0, the contents of the vector t able are loaded to the pc, and t hen program execution branches. figure 12-8 shows the flow from non-maskable interr upt request generation to acknowledgement, figure 12-9 shows the timing of non-maskable interrupt ackno wledgement, and figure 12-10 shows the acknowledgement operation when a number of non-ma skable interrupts are generated. caution during non-maskable interrupt service progr am execution, do not input another non-maskable interrupt request; if it is input, the servi ce program will be interr upted and the new non- maskable interrupt requ est will be acknowledged.
chapter 12 interrupt functions user?s manual u16995ej2v0ud 159 figure 12-8. flow from gene ration of non-maskable interrupt request to acknowledgment start wdtm4 = 1 (watchdog timer mode is selected) interval timer no wdt overflows no yes reset processing no yes yes interrupt request is generated interrupt servicing starts wdtm3 = 0 (non-maskable interrupt is selected) wdtm: watchdog timer mode register wdt: watchdog timer figure 12-9. timing of non-maskable interrupt request acknowledgment instruction instruction saving psw and pc, and jump to interrupt servicing interrupt servicing program cpu processing wdtif figure 12-10. non-maskable inte rrupt request acknowledgment second interrupt servicing first interrupt servicing nmi request (second) nmi request (first) main routine
chapter 12 interrupt functions 160 user?s manual u16995ej2v0ud 12.4.2 maskable interrupt re quest acknowledgment operation a maskable interrupt request can be acknowledged when the interrupt request flag is set to 1 and the corresponding interrupt mask flag is cleared to 0. a vect ored interrupt request is a cknowledged in the interrupt enabled status (when the ie flag is set to 1). the time required to start the interrupt servicing afte r a maskable interrupt request has been generated is shown in table 12-3. refer to figures 12-12 and 12-13 for the ti ming of interrupt request acknowledgement. table 12-3. time from generation of maskable interrupt request to servicing minimum time maximum time note 9 clocks 19 clocks note the wait time is maximum when an inte rrupt request is generat ed immediately before bt or bf instruction. remark 1 clock: (f cpu : cpu clock) when two or more maskable interrupt requests are generat ed at the same time, they are acknowledged starting from the one assigned the highest priority by the priority specification flag. a pending interrupt is acknowledged when the st atus where it can be acknowledged is set. figure 12-11 shows the algorithm of interrupt request acknowledgement. when a maskable interrupt request is a cknowledged, the psw and pc are saved to the stack in that order, the ie flag is reset to 0, and the data in the vector table determined for each in terrupt request is loaded to the pc, and execution branches. to return from interrupt servic ing, use the reti instruction. figure 12-11. interrupt request acknowledgment pr ogram algorithm start xxif = 1? xxmk = 0? ie = 1? vectored interrupt servicing yes (interrupt request generated) yes yes no no no interrupt request pending interrupt request pending xxif: interrupt request flag xxmk: interrupt mask flag ie: flag to control maskable interrupt reques t acknowledgement (1 = enable, 0 = disable) 1 f cpu
chapter 12 interrupt functions user?s manual u16995ej2v0ud 161 figure 12-12. interrupt request ackno wledgment timing (example: mov a, r) clock cpu mov a, r saving psw and pc, and jump to interrupt servicing 8 clocks interrupt servicing program interrupt if the interrupt request has generated an interrupt request flag (xxif) by t he time the instruction clocks under execution, n clocks (n = 4 to 10), are n ? 1, interrupt request acknowledgment processing will start following the completion of the instruction under exec ution. figure 12-12 shows an example us ing the 8-bit data transfer instruction mov a, r. because this instruction is executed in 4 clocks, if an interrupt request is generated bet ween the start of execution and the 3rd clock, interrupt request acknowledgment processing will ta ke place following the completion of mov a, r. figure 12-13. interrupt re quest acknowledgment timing (when interrupt request flag is gene rated in final clock under execution) clock cpu nop mov a, r saving psw and pc, and jump to interrupt servicing interrupt servicing program interrupt 8 clocks if the interrupt request flag (xxif) is gener ated in the final clock of the instru ction, interrupt request acknowledgment processing will begin after execution of t he next instruction is complete. figure 12-13 shows an example whereby an interrupt request was generated in the 2nd clock of nop (a 2-clock instruction). in this case, the interrupt request will be serv iced after execution of mov a, r, which follows nop, is complete. caution when interrupt request flag register 0 (if0), or interrupt mask flag register 0 (mk0) is being accessed, interrupt requests will be held pending. 12.4.3 multiple interrupt servicing multiple interrupts, in which another interrupt request is acknowledged while an interrupt request being serviced, can be serviced using the priority order. if multiple interr upts are generated at the same ti me, they are serviced in the order according to the priority assigned to each interrupt request in advance (refer to table 12-1 ).
chapter 12 interrupt functions 162 user?s manual u16995ej2v0ud figure 12-14. example of multiple interrupts example 1. acknowledging multiple interrupts intyy ei main servicing ei intyy servicing intxx servicing reti ie = 0 intxx reti ie = 0 the interrupt request intyy is ackno wledged during the servicing of interrupt intxx and multiple interrupts are performed. before each interrupt reques t is acknowledged, the ei instruction is issued and the interrupt request is enabled. example 2. multiple interrupts are not performed because interrupts are disabled intyy ei main servicing reti intyy servicing intxx servicing ie = 0 intxx reti intyy is held pending ie = 0 because interrupt requests are disabled (the ei instruction has not been issued) in the interrupt intxx servicing, the interrupt request intyy is not a cknowledged and multiple interrupts are not performed. intyy is held pending and is acknowledged after intxx servicing is completed. ie = 0: interrupt requests disabled
chapter 12 interrupt functions user?s manual u16995ej2v0ud 163 12.4.4 putting interrupt requests on hold if an interrupt request (such as a maskable, non-maskable, or external interrupt) is generated when a certain type of instruction is being execut ed, the interrupt request will not be acknowledged until the instruct ion is completed. such instructions (interrupt request pendi ng instructions) are as follows. ? instructions that manipulate in terrupt request flag register 0 (if0) ? instructions that manipulate in terrupt mask flag register 0 (mk0)
164 user?s manual u16995ej2v0ud chapter 13 standby function 13.1 standby function and configuration the standby function is to reduce the power consumpti on of the system and can be e ffected in the following two modes: (1) halt mode this mode is set when the halt inst ruction is executed. the halt mode stops the operation clock of the cpu. the system clock oscillator continues oscillating. this mode does not reduc e the operating current as much as the stop mode, but is useful for resumi ng processing immediately when an interrupt request is generated, or for intermittent operations. (2) stop mode this mode is set when the stop instruction is exec uted. the stop mode stops the main system clock oscillator and stops the entire system. the power consumpti on of the cpu can be s ubstantially reduced in this mode. the data memory can be reta ined at the low voltage (v dd = 1.8 v). therefore, this mode is useful for retaining the contents of t he data memory at an extremely low operating current. the stop mode can be released by an interrupt request, so that this mode can be used for intermittent operation. however, some time is required until the system clock oscilla tor stabilizes after the stop mode has been released. if processing must be resumed immedi ately by using an interrupt request, therefore, use the halt mode. in both modes, the previous contents of the registers, flags, and data memo ry before setting the standby mode are all retained. in addition, the status es of the output latch of the i/o ports and output buffer are also retained. caution to set the stop mode, be sure to stop th e operations of the periphe ral hardware, and then execute the stop instruction.
chapter 13 standby function user?s manual u16995ej2v0ud 165 13.2 register controlling standby function the wait time after the stop mode is released upon inte rrupt request until oscillation st abilizes is controlled with the oscillation stabilization time selection register (osts). osts is set with a 1-bit or 8-bit memory manipulation instruction. reset input sets osts to 04h. note that the time r equired for oscillation to stabilize after reset input varies depending on the device (refer to table 13-1 ), not depending on osts. figure 13-1. format of oscillation st abilization time selection register symbol 7 6 5 4 3 2 1 0 address after reset r/w osts 0 0 0 0 0 osts2 osts1 osts0 fffah 04h r/w osts2 osts1 osts0 0 0 0 2 12 /f x (819 s) 0 1 0 2 15 /f x (6.55 ms) 1 0 0 2 17 /f x (26.2 ms) other than above setting prohibited caution the wait time after the stop mode is released does not in clude the time from stop mode release to clock oscillation start (?a? in th e figure below), regardless of whether stop mode is released by reset input or by interr upt generation. a stop mode release x1 pin voltage waveform remarks 1. f x : main system clock oscillation frequency 2. the parenthesized values apply to operation at f x = 5.0 mhz. table 13-1. oscillation stabilization time after reset input part number oscillation stabilization time after reset input pd179322, 179322a, 179324, 179324a, 179326, 179327 2 15 /f x or 2 17 /f x (selectable using mask option) pd78f9328 2 15 /f x
chapter 13 standby function 166 user?s manual u16995ej2v0ud 13.3 standby function operation 13.3.1 halt mode (1) halt mode the halt mode is set by exec uting the halt instruction. the operation status in the halt mode is shown in the following table. table 13-2. operation statuses in halt mode halt mode operation status during main system clock operation halt mode operation status during subsystem clock operation item subsystem clock operating subsystem clock stopped main system clock operating main system clock stopped main system clock can be oscillated oscillation stopped cpu operation stopped ports (output latches) status before halt mode setting retained 8-bit timer 30, 40 operable operation stopped watch timer operable operable note 1 operable operable note 2 watchdog timer operable operation stopped power-on-clear circuit operable key return circuit operable note 3 serial interface 10 (provided in the pd78f9328 only) operable operable note 4 lcd controller/driver operable note 5 operable notes 1, 5 operable note 5 operable notes 2, 5 external interrupts operable note 3 notes 1. operation is enabled when the ma in system clock is selected 2. operation is enabled when the subsystem clock is selected 3. operation is enabled only for a maskabl e interrupt that is not masked 4. operation is enabled only when an external clock is selected 5. the halt instruction can be set a fter display instruction execution
chapter 13 standby function user?s manual u16995ej2v0ud 167 (2) releasing halt mode the halt mode can be released by the following three types of sources: (a) releasing by unmasked interrupt request the halt mode is released by an unm asked interrupt request. in this case, if the interrupt is enabled to be acknowledged, vectored interrupt processing is performed. if the inte rrupt is disabled, the instruction at the next address is executed. figure 13-2. releasing halt mode by interrupt halt instruction standby release signal wait wait halt mode operation mode operation mode clock oscillation remarks 1. the broken line indicates the case where the in terrupt request that has released the standby mode is acknowledged. 2. the wait time is as follows: ? when vectored interrupt proce ssing is performed: 9 to 10 clocks ? when vectored interrupt processi ng is not performed: 1 to 2 clocks (b) releasing by non-maskable interrupt request the halt mode is released regardl ess of whether the interrupt is enabled or disabled, and vectored interrupt processing is performed.
chapter 13 standby function 168 user?s manual u16995ej2v0ud (c) releasing by reset input when the halt mode is released by the reset signal, execution branc hes to the reset vector address in the same manner as the ordinary reset oper ation, and program exec ution is started. figure 13-3. releasing halt mode by reset input halt instruction reset signal wait note reset period halt mode operation mode oscillation stabilization wait status clock operation mode oscillation stops oscillation oscillation note 2 15 /f x : 6.55 ms (@ f x = 5.0 mhz operation) remark f x : main system clock oscillation frequency table 13-3. operation after releasing halt mode releasing source mk ie operation 0 0 executes next address instruction 0 1 executes interrupt servicing maskable interrupt request 1 retains halt mode non-maskable interrupt request ? executes interrupt servicing reset input - ? - ? reset processing : don?t care
chapter 13 standby function user?s manual u16995ej2v0ud 169 13.3.2 stop mode (1) setting and operation st atus of stop mode the stop mode is set by exec uting the stop instruction. caution because the standby mode can be released by an interrupt request signal, the standby mode is released as soon as it is set if there is an interrupt source whose interrupt request flag is set and interrupt mask flag is reset. when the stop mode is set, therefore, the halt mode is set immediately after the stop instruction has been execu ted, the wait time set by the oscillation stabilization time select ion register (osts) elapses, and then an operation mode is set. the operation status in the stop m ode is shown in the following table. table 13-4. operation statuses in stop mode stop mode operation status duri ng main system clock operation item subsystem clock operating subsystem clock stopped main system clock oscillation stopped cpu operation stopped ports (output latches) status before stop mode setting retained 8-bit timer 30, 40 operation stopped watch timer operable note 1 operation stopped watchdog timer operation stopped power-on-clear circuit operable key return circuit operable note 2 serial interface 10 (provided in the pd78f9328 only) operable note 3 lcd controller/driver operable note 1 operation stopped note 4 external interrupts operable note 2 notes 1. operation is enabled when the s ubsystem clock is selected. 2. operation is enabled only for a maskabl e interrupt that is not masked. 3. operation is enabled only when an external clock is selected. 4. before selecting the stop mode, disable display and select the static mode (refer to 10.3 (1) lcd display mode register 0 (lcdm0) ).
chapter 13 standby function 170 user?s manual u16995ej2v0ud (2) releasing stop mode the stop mode can be released by the following two types of sources: (a) releasing by unmasked interrupt request the stop mode can be released by an unmasked interrupt request. in this case, if the interrupt is enabled to be acknowledged, vectored interrupt pr ocessing is performed, after the oscillation stabilization time has elapsed. if the interrupt is dis abled, the instruction at t he next address is executed. figure 13-4. releasing stop mode by interrupt stop instruction standby release signal wait (set time by osts) stop mode operation mode oscillation stabilization wait status clock operation mode oscillation stops oscillation oscillation remark the broken line indicates the case where the inte rrupt request that has re leased the standby mode is acknowledged.
chapter 13 standby function user?s manual u16995ej2v0ud 171 (b) releasing by reset input when the stop mode is released by the reset signal, the reset operation is performed after the oscillation stabilization time has elapsed. figure 13-5. releasing stop mode by reset input stop instruction reset signal wait note stop mode operation mode oscillation stabilization wait status clock operation mode oscillation stops oscillation oscillation reset period note 2 15 /f x : 6.55 ms (@ f x = 5.0 mhz operation) remark f x : main system clock oscillation frequency table 13-5. operation after releasing stop mode releasing source mk ie operation maskable interrupt request 0 0 ex ecutes next address instruction 0 1 executes interrupt servicing 1 retains stop mode reset input ? - ? - reset processing : don?t care
172 user?s manual u16995ej2v0ud chapter 14 reset function the following three operations are av ailable to generate reset signals. (1) external reset signal input via reset pin (2) internal reset by detection of watc hdog timer inadvertent program loop time (3) internal reset using power-on-clear circuit (poc note ) the external and internal reset signals are functionally equivalent. when reset is input, program execution begins from the addresses written at addresses 0000h and 0001h. if a low-level signal is applied to the reset pin, or if the watchdog timer overflows, a reset occurs, causing each item of the hardware to enter the states listed in t able 14-1. while a reset is being applied, or while the oscillation frequency is stabilizing immediately after the end of a rese t sequence, each pin remains in the high-impedance state. if a high-level signal is applied to the reset pin, t he reset sequence is terminated, and program execution is started after the oscillation stabilizati on time has elapsed. a reset sequence caused by a watchdog timer overflow is terminated automatically and pr ogram execution is started after the o scillation stabilization time has elapsed. reset by power-on-clear (poc note ) is cleared if the supply voltage rises beyond a specific leve l, and the program execution is started after the osc illation stabilization time has elapsed. note enabled in mask rom versions ( pd179322, 179322a, 179324, 179324a, 179326, and 179327) only when poc circuit usage is selected by a mask option. cautions 1. for an external reset, input a low level for 10 s or more to the reset pin. 2. when the stop mode is cleared by reset, the stop mode contents are held during reset input. however, the port pins become high impedance. 3. in the case of mask rom versi ons, the oscillation stabilization ti me after reset input or the release of stop mode by poc can be selected from 2 15 /f x or 2 17 /f x by mask option (refer to chapter 16 mask options). in the case of the pd78f9328, only 2 15 /f x can be set because the mask option is not available. figure 14-1. block diagram of reset function reset interrupt function count clock reset controller watchdog timer power-on-clear circuit over- flow reset signal v dd stop
chapter 14 reset function user?s manual u16995ej2v0ud 173 figure 14-2. reset timing by reset input x1 reset internal reset signal port pin during normal operation delay delay hi-z reset period (oscillation stops) normal operation (reset processing) oscillation stabilization time wait figure 14-3. reset timing by overflow in watchdog timer x1 overflow in watchdog timer internal reset signal port pin hi-z during normal operation reset period (oscillation continues) normal operation (reset processing) oscillation stabilization time wait figure 14-4. reset timing by reset input in stop mode x1 reset internal reset signal port pin delay delay hi-z stop instruction execution during normal operation reset period (oscillation stops) stop status (oscillation stops) normal operation (reset processing) oscillation stabilization time wait
chapter 14 reset function 174 user?s manual u16995ej2v0ud figure 14-5. reset timing by power-on clear (a) at power application hi-z port pin reset period (oscillation stops) oscillation stabilization time wait normal operation (reset processing) x1 v dd internal reset signal power-on-clear voltage (v poc ) (b) in stop mode hi-z during normal operation port pin reset period (oscillation stops) stop status (oscillation stops) oscillation stabilization time wait normal operation (reset processing) x1 v dd internal reset signal power-on-clear voltage (v poc ) stop instruction execution (c) in normal operation mode (including halt mode) hi-z during normal operation port pin reset period (oscillation stops) oscillation stabilization time wait normal operation (reset processing) x1 v dd internal reset signal power-on-clear voltage (v poc )
chapter 14 reset function user?s manual u16995ej2v0ud 175 table 14-1. hardware status after reset hardware status after reset program counter (pc) note 1 contents of reset vector table (0000h, 0001h) set stack pointer (sp) undefined program status word (psw) 02h data memory undefined note 2 ram general-purpose registers undefined note 2 ports (p0 to p2, p4, p6, p8) (output latches) 00h port mode registers (pm0 to pm2, pm4, pm6) ffh port mode register 8 (pm8) 3fh port function register 8 (pf8) 00h pull-up resistor option registers (pu0, pub2) 00h processor clock control register (pcc) 02h suboscillation mode register (sckm) 00h subclock control register (css) 00h oscillation stabilization time selection register (osts) 04h timer counters (tm30, tm40) 00h compare registers (cr30, cr40, crh40) undefined mode control registers (tmc30, tmc40) 00h 8-bit timer 30, 40 carrier generator output control register (tca40) 00h watch timer mode control register (wtm) 00h mode register (wdtm) 00h watchdog timer clock selection register (tcl2) 00h serial operation mode register 10 (csim10) note 3 00h serial interface 10 ( provided in the pd78f9328 only) transmit/receive shift register 10 (sio10) note 3 undefined display mode register 0 (lcdm0) 00h lcd controller/driver clock control register 0 (lcdc0) 00h power-on-clear circuit power-on- clear register 1 (pocf1) 00h note 4 request flag register 0 (if0) 00h mask flag register 0 (mk0) ffh external interrupt mode register 0 (intm0) 00h interrupts key return mode register 00 (krm00) 00h notes 1. while a reset signal is being input, and during the osc illation stabilization time wa it, only the contents of the pc will be undefined; the remai nder of the hardware will be the same state as after reset. 2. in standby mode, ram enters the hold state after reset. 3. provided in the pd78f9328 only 4. the value is 04h only after a power-on-clear reset.
176 user?s manual u16995ej2v0ud chapter 15 pd78f9328 the pd78f9328 is available as the fl ash memory version of the pd179327 subseries. the pd78f9328 is a version with t he internal rom of the pd179322, 179322a, 179324, 179324a, 179326, 179327 replaced with flash memory. the differences between the pd78f9328 and the mask rom versions are shown in table 15-1. table 15-1. differences between pd78f9328 and mask rom versions flash memory version mask rom version part number item pd78f9328 pd179322 pd179322a pd179324 pd179324a pd179326 pd179327 rom 32 kb (flash memory) 4 kb 8 kb 16 kb 24 kb high-speed ram 512 bytes 256 bytes 512 bytes internal memory lcd display ram 24 4 bits ic0 pin not provided provided v pp pin provided not provided serial interface 10 provided not provided power-on clear (poc) circuit always operates use is selected by mask option oscillation stabilization wait time after stop mode is released by reset or poc fixed to 2 15 /f x 2 15 /f x or 2 17 /f x selected by mask option power supply voltage v dd = 1.8 to 5.5 v v dd = 1.8 to 3.6 v electrical s pecifications refer to chapter 18 electrical specifications ( pd179322, 179322a, 179324, 179324a, 179326, and 179327) and chapter 19 electrical specifications ( pd78f9328) caution there are differences in noi se immunity and noise radiation be tween the flash memory and mask rom versions. when pre-producing an applicati on set with the flash memory version and then mass-producing it with the mask rom version, be sure to conduct suffici ent evaluations for the commercial samples (not engineering samples) of the mask rom version.
chapter 15 pd78f9328 user?s manual u16995ej2v0ud 177 15.1 flash memory characteristics flash memory programming is performed by connecting a dedi cated flash programmer (flashpro iv (part no. fl- pr4, pg-fp4)) to the target system wit h the flash memory mounted on the target system (on-board). a flash memory writing adapter (program adapter), whic h is a target board used exclusively for programming, is also provided. remark fl-pr4, and the program adapter are the products made by naito densei machida mfg. co., ltd. (tel +81-45-475-4191). programming using flash memory has the following advantages. ? software can be modified after the microcont roller is solder-mounted on the target system. ? distinguishing software facilities low-quantity, varied model production ? easy data adjustment when starting mass production 15.1.1 programming environment the following shows the environment required for pd78f9328 flash memory programming. when flashpro iii/flashpro iv is used as a dedicated flash programmer, a host machine is required to control the dedicated flash programmer. communi cation between the host machine and flash programmer is performed via rs- 232c/usb (rev.1.1). for details, refer the manuals for flashpro iv. figure 15-1. environment for wr iting program to flash memory host machine rs-232c usb dedicated flash programmer pd78f9328 v pp v dd v ss reset 3-wire serial i/o
chapter 15 pd78f9328 178 user?s manual u16995ej2v0ud 15.1.2 communication mode use the communication mode shown in table 15-2 to perform communication between the dedicated flash programmer and pd78f9328. table 15-2. communication mode list type setting note 1 cpu clock communication mode comm port sio clock in flashpro on target board multiple rate pins used number of v pp pulses 3-wire serial i/o sio ch-0 (3-wired, sync) 100 hz to 1.25 mhz note2 1, 2, 4, 5 mhz notes 2, 3 1 to 5 mhz note 2 1.0 sck10/p20 so10/p21 si10/p22 0 notes 1. selection items for type settings on the dedicated fl ash programmer (flashpro iv (part no. fl-pr4, pg-fp4)). 2. the possible setting range differs depending on the voltage. for details, refer to chapter 19 electrical specifications ( pd78f9328). caution be sure to select a communicat ion mode depending on the number of v pp pulses shown in table 15-2. figure 15-2. communication mode selection format 10 v v ss v dd v pp v dd v ss reset 12 n v pp pulses
chapter 15 pd78f9328 user?s manual u16995ej2v0ud 179 figure 15-3. example of connecti on with dedicated flash programmer v pp v dd /reset sck so/txd si/rxd clk note gnd v pp v dd reset sck10 si10 so10 x1 v ss pd78f9328 dedicated flash programmer note connect this pin when the system clock is supplied by dedicated flash programmer. if an oscillator is already connected to the x1 pin, do not connect to the clk pin. caution the v dd pin, if already connected to the power suppl y, must be connected to the vdd pin of the dedicated flash programmer. before us ing the power supply connected to the v dd pin, supply voltage before starting programming. if flashpro iii/flashpro iv is used as a dedicated flas h programmer, the following signals are generated for the pd78f9328. for details, refer to t he manual of flashpro iii/flashpro iv. table 15-3. pin connection list signal name i/o pin function pi n name 3-wire serial i/o vpp1 output write voltage v pp vpp2 ? ? vdd i/o v dd voltage generation v dd note gnd ? ground v ss clk output clock output x1 reset output reset signal reset si input reception signal so10 so output transmit signal si10 sck output transfer clock sck10 hs ? ? ? note v dd voltage must be supplied befor e programming is started. remark : pin must be connected. : if the signal is supplied on the target board, pin need not be connected. : pin need not be connected.
chapter 15 pd78f9328 180 user?s manual u16995ej2v0ud 15.1.3 on-board pin processing when performing programming on the tar get system, provide a connector on t he target system to connect the dedicated flash programmer. an on-board function that allows switching between normal operation m ode and flash memory programming mode may be required in some cases. in normal operation mode, input 0 v to the v pp pin. in flash memory progra mming mode, a writ e voltage of 10.0 v (typ.) is supplied to the v pp pin, so perform the following. (1) connect a pull-down resistor (rv pp = 10 k ? ) to the v pp pin. (2) use the jumper on t he board to switch the v pp pin input to either the wr iter or directly to gnd. a v pp pin connection example is shown below. figure 15-4. v pp pin connection example pd78f9328 v pp connection pin of dedicated flash programmer pull-down resistor (rv pp ) the following shows the pins us ed by the serial interface. serial interface pins used 3-wire serial i/o sck10, so10, si10 when connecting the dedicated flash programmer a serial interface pin that is c onnected to another device on- board, signal conflict or abnormal operati on of the other devices may occur. care must therefore be taken with such connections.
chapter 15 pd78f9328 user?s manual u16995ej2v0ud 181 (1) signal conflict if the dedicated flash programmer (output ) is connected to a serial interfac e pin (input) that is connected to another device (output), a signal conflict occurs. to prevent this, isolate the connection wi th the other device or set the other device to the output high impedance status. figure 15-5. signal conflict (input pin of serial interface) input pin signal conflict connection pin of dedicated flash programmer other device output pin in the flash memory programming mode, the signal output by another device and the signal sent by the dedicated flash programmer conflict, therefore, isolate the signal of the other device. pd78f9328 (2) abnormal operation of other device if the dedicated flash programmer (output or input) is connected to a serial interface pin (input or output) that is connected to another device (input ), a signal is output to the dev ice, and this may cause an abnormal operation. to prevent this abnormal oper ation, isolate the connection with t he other device or set so that the input signals to the ot her device are ignored. figure 15-6. abnormal operation of other device pin connection pin of dedicated flash programmer other device input pin if the signal output by the pd78f9328 affects another device in the flash memory programming mode, isolate the signals of the other device. pin connection pin of dedicated flash programmer other device input pin if the signal output by the dedicated flash programmer affects another device in the flash memory programming mode, isolate the signals of the other device. pd78f9328 pd78f9328
chapter 15 pd78f9328 182 user?s manual u16995ej2v0ud if the reset signal of the dedicated flash programmer is connected to the reset pin connected to the reset signal generator on-board, a signal conflict occurs. to prevent this, is olate the connection with the reset signal generator. if the reset signal is input from the user system in the flash memory programming mode, a normal programming operation cannot be performed. therefore, do not input reset signal s from other than the dedicated flash programmer. figure 15-7. signal conflict (reset pin) reset connection pin of dedicated flash programmer signal conflict output pin the signal output by the reset signal generator and the signal output from the dedicated flash programmer conflict in the flash memory programming mode, so isolate the signal of the reset signal generator. pd78f9328 when the pd78f9328 enters the flash memory programming m ode, all the pins ot her than those that communicate in flash memory programming are in the same status as immediately after reset. if the external device does not recogni ze initial statuses such as the output high impedance st atus, therefore, connect the external device to v dd or v ss via a resistor. when using the on-board clock, connect x1 and x2 as required in the normal operation mode. when using the clock output of the fl ash programmer, connect it directly to x1, disconnecting the main oscillator on-board, and leave the x2 pin open. when using the power supply output of the flash programmer, connect the v dd and v ss pins to vdd and gnd of the flash programmer, respectively. when using the on-board power supply, connect it as required in the normal operation mode. because the flash programmer monitors the voltage, however, vdd of the flash programme r must be connected.
chapter 15 pd78f9328 user?s manual u16995ej2v0ud 183 15.1.4 connection on flash memory writing adapter the following shows an example of the recommended connection when using t he flash memory writing adapter. figure 15-8. wiring example of flash memory writing adapter using 3-wire serial i/o mode 52 51 50 49 48 47 46 45 44 43 42 14 15 16 17 18 19 20 21 21 23 24 1 2 3 4 5 6 7 8 9 10 11 39 38 37 36 35 34 33 32 31 30 29 12 13 28 27 41 40 25 26 gnd v dd v dd2 si/rxd so/txd sck clk /reset v pp reserve/hs writer interface v dd (2.7 to 5.5 v) gnd
184 user?s manual u16995ej2v0ud chapter 16 mask options the mask rom versions ( pd179322, 179322a, 179324, 179324a, 179326, and 179327) have the following mask option. ? oscillation stabilization wait time the oscillation stabilization wait time after the rel ease of stop mode by reset or poc can be selected. <1> 2 15 /f x <2> 2 17 /f x caution the oscillation stabilization wait time for the flash memory version ( pd78f9328) is fixed to 2 15 /f x . ? power-on-clear (poc) circuit use/non use of the poc circuit can be selected. <1> poc circuit used <2> poc circuit not used caution the poc circuit of the flash memory version ( pd78f9328) is always used (always operating).
user?s manual u16995ej2v0ud 185 chapter 17 instruction set this chapter lists the instruction set of the pd179327 subseries. for the deta ils of the operation and machine language (instruction code) of each instruction, refer to 78k/0s series instructions user?s manual (u11047e) . 17.1 operation 17.1.1 operand identifier s and description methods operands are described in ?operands? colu mn of each instruction in accordanc e with the description method of the instruction operand identifier (refer to the assembler specifications for detail). when there are two or more description methods, select one of them. alphabetic letters in capitals and symbols, #, !, $, and [ ] are key words and are described as they are. each symbol has the following meaning. ? #: immediate data specification ? $: relative address specification ? !: absolute address specification ? [ ]: indirect address specification in the case of immediate data, descr ibe an appropriate numeric value or a label. when using a label, be sure to describe the #, !, $ and [ ] symbols. for operand register identifiers, r and rp, either functional names (x, a, c, etc.) or absolute names (names in parenthesis in the table below, r0, r1, r2, etc.) can be used for description. table 17-1. operand identifi ers and description methods identifier description method r rp sfr x (r0), a (r1), c (r2), b (r3), e (r4), d (r5), l (r6), h (r7) ax (rp0), bc (rp1), de (rp2), hl (rp3) special-function register symbol saddr saddrp fe20h to ff1fh immediate data or labels fe20h to ff1fh immediate data or labels (even addresses only) addr16 addr5 0000h to ffffh immediate data or labels (only ev en addresses for 16-bit data transfer instructions) 0040h to 007fh immediate data or labels (even addresses only) word byte bit 16-bit immediate data or label 8-bit immediate data or label 3-bit immediate data or label remark see table 3-3 special function registers for symbols of special function registers.
chapter 17 instruction set 186 user?s manual u16995ej2v0ud 17.1.2 description of ?operation? column a: a register; 8-bit accumulator x: x register b: b register c: c register d: d register e: e register h: h register l: l register ax: ax register pair; 16-bit accumulator bc: bc register pair de: de register pair hl: hl register pair pc: program counter sp: stack pointer psw: program status word cy: carry flag ac: auxiliary carry flag z: zero flag ie: interrupt request enable flag nmis: flag indicating non-maskable interrupt servicing in progress ( ): memory contents indicated by addre ss or register contents in parenthesis x h , x l : higher 8 bits and lower 8 bits of 16-bit register : logical product (and) : logical sum (or) v: exclusive logical sum (exclusive or) : inverted data addr16: 16-bit immediate data or label jdisp8: signed 8-bit data (displacement value) 17.1.3 description of ?flag? column (blank): unchanged 0: cleared to 0 1: set to 1 x: set/cleared according to the result r: previously saved value is restored
chapter 17 instruction set user?s manual u16995ej2v0ud 187 17.2 operation list mnemonic operands byte clock operation flag z ac cy r, #byte 3 6 r byte saddr, #byte 3 6 (saddr) byte sfr, #byte 3 6 sfr byte a, r note 1 2 4 a r r, a note 1 2 4 r a a, saddr 2 4 a (saddr) saddr, a 2 4 (saddr) a a, sfr 2 4 a sfr sfr, a 2 4 sfr a a, !addr16 3 8 a (addr16) !addr16, a 3 8 (addr16) a psw, #byte 3 6 psw byte x x x a, psw 2 4 a psw psw, a 2 4 psw a x x x a, [de] 1 6 a (de) [de], a 1 6 (de) a a, [hl] 1 6 a (hl) [hl], a 1 6 (hl) a a, [hl+byte] 2 6 a (hl + byte) mov [hl+byte], a 2 6 (hl + byte) a a, x 1 4 a ? x a, r note 2 2 6 a ? r a, saddr 2 6 a ? (saddr) a, sfr 2 6 a ? sfr a, [de] 1 8 a ? (de) a, [hl] 1 8 a ? (hl) xch a, [hl+byte] 2 8 a ? (hl + byte) notes 1. except r = a. 2. except r = a, x. remark one instruction clock cycle is one cpu clock cycle (f cpu ) selected by the processor clock control register (pcc).
chapter 17 instruction set 188 user?s manual u16995ej2v0ud mnemonic operands byte clock operation flag z ac cy movw rp, #word 3 6 rp word ax, saddrp 2 6 ax (saddrp) saddrp, ax 2 8 (saddrp) ax ax, rp note 1 4 ax rp rp, ax note 1 4 rp ax xchw ax, rp note 1 8 ax ? rp add a, #byte 2 4 a, cy a + byte x x x saddr, #byte 3 6 (saddr), cy (saddr) + byte x x x a, r 2 4 a, cy a + r x x x a, saddr 2 4 a, cy a + (saddr) x x x a, !addr16 3 8 a, cy a + (addr16) x x x a, [hl] 1 6 a, cy a + (hl) x x x a, [hl+byte] 2 6 a, cy a + (hl + byte) x x x addc a, #byte 2 4 a, cy a + byte + cy x x x saddr, #byte 3 6 (saddr), cy (saddr) + byte + cy x x x a, r 2 4 a, cy a + r + cy x x x a, saddr 2 4 a, cy a + (saddr) + cy x x x a, !addr16 3 8 a, cy a + (addr16) + cy x x x a, [hl] 1 6 a, cy a + (hl) + cy x x x a, [hl+byte] 2 6 a, cy a + (hl + byte) + cy x x x sub a, #byte 2 4 a, cy a ? byte x x x saddr, #byte 3 6 (saddr), cy (saddr) ? byte x x x a, r 2 4 a, cy a ? r x x x a, saddr 2 4 a, cy a ? (saddr) x x x a, !addr16 3 8 a, cy a ? (addr16) x x x a, [hl] 1 6 a, cy a ? (hl) x x x a, [hl+byte] 2 6 a, cy a ? (hl + byte) x x x note only when rp = bc, de, or hl. remark one instruction clock cycle is one cpu clock cycle (f cpu ) selected by the processor clock control register (pcc).
chapter 17 instruction set user?s manual u16995ej2v0ud 189 mnemonic operands byte clock operation flag z ac cy subc a, #byte 2 4 a, cy a ? byte ? cy x x x saddr, #byte 3 6 (saddr), cy (saddr) ? byte ? cy x x x a, r 2 4 a, cy a ? r ? cy x x x a, saddr 2 4 a, cy a ? (saddr) ? cy x x x a, !addr16 3 8 a, cy a ? (addr16) ? cy x x x a, [hl] 1 6 a, cy a ? (hl) ? cy x x x a, [hl+byte] 2 6 a, cy a ? (hl + byte) ? cy x x x and a, #byte 2 4 a a byte x saddr, #byte 3 6 (saddr) (saddr) byte x a, r 2 4 a a r x a, saddr 2 4 a a (saddr) x a, !addr16 3 8 a a (addr16) x a, [hl] 1 6 a a (hl) x a, [hl+byte] 2 6 a a (hl + byte) x or a, #byte 2 4 a a byte x saddr, #byte 3 6 (saddr) (saddr) byte x a, r 2 4 a a r x a, saddr 2 4 a a (saddr) x a, !addr16 3 8 a a (addr16) x a, [hl] 1 6 a a (hl) x a, [hl+byte] 2 6 a a (hl + byte) x xor a, #byte 2 4 a a v byte x saddr, #byte 3 6 (saddr) (saddr) v byte x a, r 2 4 a a v r x a, saddr 2 4 a a v (saddr) x a, !addr16 3 8 a a v (addr16) x a, [hl] 1 6 a a v (hl) x a, [hl+byte] 2 6 a a v (hl + byte) x remark one instruction clock cycle is one cpu clock cycle (f cpu ) selected by the processor clock control register (pcc).
chapter 17 instruction set 190 user?s manual u16995ej2v0ud mnemonic operands byte clock operation flag z ac cy cmp a, #byte 2 4 a ? byte x x x saddr, #byte 3 6 (saddr) ? byte x x x a, r 2 4 a ? r x x x a, saddr 2 4 a ? (saddr) x x x a, !addr16 3 8 a ? (addr16) x x x a, [hl] 1 6 a ? (hl) x x x a, [hl+byte] 2 6 a ? (hl + byte) x x x addw ax, #word 3 6 ax, cy ax + word x x x subw ax, #word 3 6 ax, cy ax ? word x x x cmpw ax, #word 3 6 ax ? word x x x inc r 2 4 r r + 1 x x saddr 2 4 (saddr) (saddr) + 1 x x dec r 2 4 r r ? 1 x x saddr 2 4 (saddr) (saddr) ? 1 x x incw rp 1 4 rp rp + 1 decw rp 1 4 rp rp ? 1 ror a, 1 1 2 (cy, a 7 a 0 , a m ? 1 a m ) 1 x rol a, 1 1 2 (cy, a 0 a 7 , a m+1 a m ) 1 x rorc a, 1 1 2 (cy a 0 , a 7 cy, a m ? 1 a m ) 1 x rolc a, 1 1 2 (cy a 7 , a 0 cy, a m+1 a m ) 1 x set1 saddr.bit 3 6 (saddr.bit) 1 sfr.bit 3 6 sfr.bit 1 a.bit 2 4 a.bit 1 psw.bit 3 6 psw.bit 1 x x x [hl].bit 2 10 (hl).bit 1 clr1 saddr.bit 3 6 (saddr.bit) 0 sfr.bit 3 6 sfr.bit 0 a.bit 2 4 a.bit 0 psw.bit 3 6 psw.bit 0 x x x [hl].bit 2 10 (hl).bit 0 set1 cy 1 2 cy 1 1 clr1 cy 1 2 cy 0 0 not1 cy 1 2 cy cy x remark one instruction clock cycle is one cpu clock cycle (f cpu ) selected by the processor clock control register (pcc).
chapter 17 instruction set user?s manual u16995ej2v0ud 191 mnemonic operands byte clock operation flag z ac cy call !addr16 3 6 (sp ? 1) (pc + 3) h , (sp ? 2) (pc + 3) l , pc addr16, sp sp ? 2 callt [addr5] 1 8 (sp ? 1) (pc + 1) h , (sp ? 2) (pc + 1) l , pc h (00000000, addr5 + 1), pc l (00000000, addr5), sp sp ? 2 ret 1 6 pc h (sp + 1), pc l (sp), sp sp + 2 reti 1 8 pc h (sp + 1), pc l (sp), psw (sp + 2), sp sp + 3, nmis 0 rrr push psw 1 2 (sp ? 1) psw, sp sp ? 1 rp 1 4 (sp ? 1) rp h , (sp ? 2) rp l , sp sp ? 2 pop psw 1 4 psw (sp), sp sp + 1 r r r rp 1 6 rp h (sp + 1), rp l (sp), sp sp + 2 movw sp, ax 2 8 sp ax ax, sp 2 6 ax sp br !addr16 3 6 pc addr16 $addr16 2 6 pc pc + 2 + jdisp8 ax 1 6 pc h a, pc l x bc $saddr16 2 6 pc pc + 2 + jdisp8 if cy = 1 bnc $saddr16 2 6 pc pc + 2 + jdisp8 if cy = 0 bz $saddr16 2 6 pc pc + 2 + jdisp8 if z = 1 bnz $saddr16 2 6 pc pc + 2 + jdisp8 if z = 0 bt saddr.bit, $addr16 4 10 pc pc + 4 + jdisp8 if (saddr.bit) = 1 sfr.bit, $addr16 4 10 pc pc + 4 + jdisp8 if sfr.bit = 1 a.bit, $addr16 3 8 pc pc + 3 + jdisp8 if a.bit = 1 psw.bit, $addr16 4 10 pc pc + 4 + jdisp8 if psw.bit = 1 bf saddr.bit, $addr16 4 10 pc pc + 4 + jdisp8 if (saddr.bit) = 0 sfr.bit, $addr16 4 10 pc pc + 4 + jdisp8 if sfr.bit = 0 a.bit, $addr16 3 8 pc pc + 3 + jdisp8 if a.bit = 0 psw.bit, $addr16 4 10 pc pc + 4 + jdisp8 if psw.bit = 0 dbnz b, $addr16 2 6 b b ? 1, then pc pc + 2 + jdisp8 if b 0 c, $addr16 2 6 c c ? 1, then pc pc + 2 + jdisp8 if c 0 saddr, $addr16 3 8 (saddr) (saddr) ? 1, then pc pc + 3 + jdisp8 if (saddr) 0 nop 1 2 no operation ei 3 6 ie 1 (enable interrupt) di 3 6 ie 0 (disable interrupt) halt 1 2 set halt mode stop 1 2 set stop mode remark one instruction clock cycle is one cpu clock cycle (f cpu ) selected by the processor clock control register (pcc).
chapter 17 instruction set 192 user?s manual u16995ej2v0ud 17.3 instructions listed by addressing type (1) 8-bit instructions mov, xch, add, addc, sub, subc, and, or, xor, cmp, inc, dec, ror, rol, rorc, rolc, push, pop, dbnz 2nd operand 1st operand #byte a r sfr saddr !addr16 psw [de] [hl] [hl+byte] $addr1 6 1 none a add addc sub subc and or xor cmp mov note xch note add addc sub subc and or xor cmp mov xch mov xch add addc sub subc and or xor cmp mov add addc sub subc and or xor cmp mov mov xch mov xch add addc sub subc and or xor cmp mov xch add addc sub subc and or xor cmp ror rol rorc rolc r mov mov inc dec b, c dbnz sfr mov mov saddr mov add addc sub subc and or xor cmp mov dbnz inc dec !addr16 mov psw mov mov push pop [de] mov [hl] mov [hl+byte] mov note except r = a.
chapter 17 instruction set user?s manual u16995ej2v0ud 193 (2) 16-bit instructions movw, xchw, addw, subw, cmpw , push, pop, incw, decw 2nd operand 1st operand #word ax rp note saddrp sp none ax addw subw cmpw movw xchw movw movw rp movw movw note incw decw push pop saddrp movw sp movw note only when rp = bc, de, or hl. (3) bit manipulation instructions set1, clr1, not1, bt, bf 2nd operand 1st operand $addr16 none a.bit bt bf set1 clr1 sfr.bit bt bf set1 clr1 saddr.bit bt bf set1 clr1 psw.bit bt bf set1 clr1 [hl].bit set1 clr1 cy set1 clr1 not1
chapter 17 instruction set 194 user?s manual u16995ej2v0ud (4) call instructions/branch instructions call, callt, br, bc, bnc, bz, bnz, dbnz 2nd operand 1st operand ax !addr16 [addr5] $addr16 basic instructions br call br callt br bc bnc bz bnz compound instructions dbnz (5) other instructions ret, reti, nop, ei, di, halt, stop
user?s manual u16995ej2v0ud 195 chapter 18 electrical specifications ( pd179322, 179322a, 179324, 179324a, 179326, and 179327) absolute maximum ratings (t a = 25 c) parameter symbol conditions ratings unit v dd ? 0.3 to +6.5 v supply voltage v lc0 ? 0.3 to +6.5 v input voltage v i ? 0.3 to v dd + 0.3 note v v o1 p00 to p03, p10, p11, p20 to p22, p40 to p43, p60, p61 ? 0.3 to v dd + 0.3 note v output voltage v o2 com0 to com3, s0 to s16, p80/s22 to p85/s17, s23 ? 0.3 to v lc0 + 0.3 note v pin p60/to40 ? 30 ma per pin (except p60/to40) ? 10 ma output current, high i oh total for all pins (except p60/to40) ? 30 ma per pin 30 ma output current, low i ol total for all pins 80 ma operating ambient temperature t a ? 40 to +85 c storage temperature t stg ? 65 to +150 c note 6.5 v or less caution product quality may suffer if the absolute maximum rating is exceeded even momentarily for any parameter. that is, the absolute maximum rati ngs are rated values at which the product is on the verge of suffering physical damage, and therefore the product must be used under conditions that ensure that the abso lute maximum ratings are not exceeded. remark unless specified otherwise, the characteristics of alternate-functi on pins are the same as those of port pins.
chapter 18 electrical specifications ( pd179322, 179322a, 179324, 179324a, 179326, and 179327) 196 user?s manual u16995ej2v0ud main system clock oscillator characteristics (t a = ? 40 to +85c, v dd = 1.8 to 3.6 v) resonator recommended circuit parameter conditions min. typ. max. unit oscillation frequency (f x ) note 1 1.0 5.0 mhz ceramic resonator x1 x2 c1 c2 oscillation stabilization time note 2 after v dd has reached the oscillation voltage range min. 4 ms oscillation frequency note 1 1.0 5.0 mhz crystal resonator x1 x2 c1 c2 oscillation stabilization time note 2 30 ms x1 input frequency (f x ) note 1 1.0 5.0 mhz external clock x1 x2 x1 input high-/low- level width (t xh , t xl ) 85 500 ns notes 1. indicates only oscillator c haracteristics. refer to ac characteristics for instruction execution time. 2. time required to stabilize oscillation after reset or stop mode release. use t he resonator to stabilize oscillation within the oscillation wait time. cautions 1. when using the ma in system clock oscillator, wire as fo llows in the area enclosed by the broken lines in the above fi gures to avoid an adverse eff ect from wiring capacitance. ? keep the wiring length as short as possible. ? do not cross the wiring with other signal lines. ? do not route the wiring near a signal line th rough which a high fluctuating current flows. ? always make the ground point of the osc illator capacitor the same potential as v ss . ? do not ground the capacitor to a ground patte rn through which a high current flows. ? do not fetch signals from the oscillator. 2. when the main system clock is stopped a nd the device is operating on the subsystem clock, wait until the oscillation stabilization time has been secured by the program before switching back to the main system clock.
chapter 18 electrical specifications ( pd179322, 179322a, 179324, 179324a, 179326, and 179327) user?s manual u16995ej2v0ud 197 recommended oscillation circuit constants ceramic oscillator (t a = ? 40 to +85 c) (mask rom version) recommended circuit constant (pf) oscillation voltage range (v dd ) manufacturer part number frequency (mhz) c1 c2 min. max. remark csbla1m00j58-b0 note csbfb1m00j58-r1 note 1.0 100 100 rd = 1.5 k ? cstcc2m00g56-r0 cstls2m00g56-b0 2.0 1.9 3.6 cstcr4m00g53-r0 1.8 3.6 cstls4m00g53-b0 4.0 1.9 3.6 cstcr4m19g53-r0 1.8 3.6 cstls4m19g53-b0 4.194 cstcr4m91g53-r0 cstls4m91g53-b0 4.915 cstcr5m00g53-r0 murata mfg. (standard product) cstls5m00g53-b0 5.0 ? ? 1.9 3.6 with internal capacitor cstls4m00g53093-b0 4.0 cstls4m19g53093-b0 4.194 cstcr4m91g53093-r0 cstls4m91g53093-b0 4.915 cstcr5m00g53093-r0 murata mfg. (low-voltage drive type) cstls5m00g53093-b0 5.0 ? ? 1.8 3.6 with internal capacitor fcr4.0mc5 4.0 tdk fcr5.0mc5 5.0 ? ? 2.2 3.6 with internal capacitor note when using the csbla1m00j58-b0 or csbfb1m00j58- r1 (1.0 mhz) of murata mfg. as the ceramic oscillator, a limiting resistor (rd = 1.5 k ? ) is necessary (refer to the figure bel ow). the limiting resistor is not necessary when other recommended oscillators are used. x2 x1 c2 c1 csbla1m00j58-b0 csbfb1m00j58-r1 rd caution the oscillator cons tant is a reference value based on eval uation under a specific environment by the resonator manufacturer. if optimization of oscillator characteristics is necessary in the actual app lication, apply to the resonator manufacturer for evaluati on on the implementation circuit. the oscillation voltage and osc illation frequency indicate only osc illator characteristics. use the pd179327 subseries so that the in ternal operating conditions are within the specifications of the dc and ac characteristics.
chapter 18 electrical specifications ( pd179322, 179322a, 179324, 179324a, 179326, and 179327) 198 user?s manual u16995ej2v0ud remark for the resonator selecti on and oscillator constant of pd179322a and 179324a, users are required to either evaluate the oscillation t hemselves or apply to the resonat or manufacturer for evaluation. subsystem clock oscillator characteristics (t a = ? 40 to +85c, v dd = 1.8 to 3.6 v) resonator recommended circuit parameter conditions min. typ. max. unit oscillation frequency (f xt ) note 1 32 32.768 35 khz crystal resonator oscillation stabilization time note 2 10 s xt1 input frequency (f xt ) note 1 32 35 khz external clock xt1 xt2 xt1 input high-/low- level width (t xth , t xtl ) 14.3 15.6 s notes 1. indicates only oscillator char acteristics. refer to ac characteristics for instruction execution time. 2. the time required for oscillation to stabilize after v dd reaches the min. oscilla tion voltage range. use a resonator to stabilize oscillation during the oscillation wait time. cautions 1. when using the s ubsystem clock oscillator, wire as follo ws in the area enclosed by the broken lines in the above fi gures to avoid an adverse eff ect from wiring capacitance. ? keep the wiring length as short as possible. ? do not cross the wiring with the other signal lines. ? do not route the wiring near a signal line th rough which a high fluctuating current flows. ? always make the ground point of the osc illator capacitor the same potential as v ss . ? do not ground the capacitor to a ground patte rn through which a high current flows. ? do not fetch signals from the oscillator. 2. the subsystem clock osc illator is designed as a low-amplit ude circuit for reducing current consumption, and is more pr one to malfunction due to noise than the main system clock oscillator. particular care is therefore re quired with the wiring method when the subsystem clock is used. remark for the resonator selection and oscillator constant, users are required to eit her evaluate the oscillation themselves or apply to the resonat or manufacturer for evaluation. xt2 xt1 c4 c3 r
chapter 18 electrical specifications ( pd179322, 179322a, 179324, 179324a, 179326, and 179327) user?s manual u16995ej2v0ud 199 dc characteristics (t a = ? 40 to +85c, v dd = 1.8 to 3.6 v) (1/2) parameter symbol conditions min. typ. max. unit per pin 10 ma output current, low i ol total for all pins 80 ma per pin (except p60/to40) ? 1 ma p60/to40 v dd = 3.0 v, v oh = 2.0 v ? 7 ? 15 ? 24 ma output current, high i oh total for all pins (except p60/to40) ? 15 ma 2.7 v dd 3.6 v 0.7v dd v dd v v ih1 p00 to p03, p10, p11, p60, p80 to p85 1.8 v dd 3.6 v 0.9v dd v dd v 2.7 v dd 3.6 v 0.8v dd v dd v v ih2 reset, p20 to p22, p40 to p43, p61 1.8 v dd 3.6 v 0.9v dd v dd v v ih3 x1, x2 v dd ? 0.1 v dd v input voltage, high v ih4 xt1, xt2 v dd ? 0.1 v dd v 2.7 v dd 3.6 v 0 0.3v dd v v il1 p00 to p03, p10, p11, p60, p80 to p85 1.8 v dd 3.6 v 0 0.1v dd v 2.7 v dd 3.6 v 0 0.2v dd v v il2 reset, p20 to p22, p40 to p43, p61 1.8 v dd 3.6 v 0 0.1v dd v v il3 x1, x2 0 0.1 v input voltage, low v il4 xt1, xt2 0 0.1 v v oh11 1.8 v dd 3.6 v, i oh = ? 100 a v dd ? 0.5 v v oh12 p00 to p03, p10, p11, p20 to p22, p40 to p43, p61 1.8 v dd 3.6 v, i oh = ? 500 a v dd ? 0.7 v v oh21 1.8 v dd 3.6 v, i oh = ? 400 a v dd ? 0.5 v v oh22 p60/to40 1.8 v dd 3.6 v, i oh = ? 2 ma v dd ? 0.7 v v oh31 1.8 v dd 3.6 v, i oh = ? 100 a v lc0 ? 0.5 v output voltage, high v oh32 p80/s22 to p85/s17 1.8 v dd 3.6 v, i oh = ? 500 a v lc0 ? 0.7 v v ol11 1.8 v dd 3.6 v, i ol = 400 a 0.5 v v ol12 p00 to p03, p10, p11, p20 to p22, p40 to p43, p60, p61 1.8 v dd 3.6 v, i ol = 2 ma 0.7 v v ol21 1.8 v lc0 3.6 v, i ol = 400 a 0.5 v output voltage, low v ol22 p80/s22 to p85/s17 1.8 v lc0 3.6 v, i ol = 2 ma 0.7 v remark unless specified otherwise, the characteristics of alternate-functi on pins are the same as those of port pins.
chapter 18 electrical specifications ( pd179322, 179322a, 179324, 179324a, 179326, and 179327) 200 user?s manual u16995ej2v0ud dc characteristics (t a = ?40 to +85c, v dd = 1.8 to 3.6 v) (2/2) parameter symbol conditions min. typ. max. unit i lih1 p00 to p03, p10, p11, p20 to p22, p40 to p43, p60, p61, reset, p80 to p85 3 a input leakage current, high i lih2 v in = v dd x1, x2, xt1, xt2 20 a i lil1 p00 to p03, p10, p11, p20 to p22, p40 to p43, p60, p61, reset, p80 to p85 ? 3 a input leakage current, low i lil2 v in = 0 v x1, x2, xt1, xt2 ? 20 a software pull-up resistors r 1 v in = 0 v p00 to p03, p10, p11, p20 to p22, p40 to p43 50 100 200 k ? i dd1 5.0 mhz crystal oscillation operating mode v dd = 3.3 v note 2 0.6 1.2 ma i dd2 5.0 mhz crystal oscillation halt mode v dd = 3.3 v 0.4 0.8 ma i dd3 32.768 khz crystal oscillation halt mode note 3 v dd = 3.3 v 7 25 a i dd4 32.768 khz crystal oscillation stopped stop mode (poc circuit used) v dd = 3.3 v 1 10 a supply current note 1 i dd5 32.768 khz crystal oscillation stopped stop mode (poc circuit not used) v dd = 3.3 v 0.05 5 a notes 1. current flowing through ports (including current flowing through on-chip pull-up resistors and from v lc0 to v ss ) is not included. 2. low-speed mode operation (when pcc is set to 02h) 3. when the main system cl ock operation is stopped. remark unless specified otherwise, the characteristics of alternate-functi on pins are the same as those of port pins.
chapter 18 electrical specifications ( pd179322, 179322a, 179324, 179324a, 179326, and 179327) user?s manual u16995ej2v0ud 201 ac characteristics (1) basic operation (t a = ? 40 to +85c, v dd = 1.8 to 3.6 v) parameter symbol conditions min. typ. max. unit 2.7 v dd 3.6 v 0.4 8.0 s cycle time (min. instruction execution time) t cy 1.8 v dd 3.6 v 1.6 8.0 s interrupt input high-/low-level width t inth , t intl int 10 s key return pin low-level width t kril kr00 to kr03 10 s reset low-level width t rsl 10 s t cy vs. v dd (main system clock) supply voltage v dd (v) 123456 0.1 0.4 0.5 1.0 2.0 10 20 60 cycle time t cy [ s] guaranteed operation range
chapter 18 electrical specifications ( pd179322, 179322a, 179324, 179324a, 179326, and 179327) 202 user?s manual u16995ej2v0ud ac timing measurement points (excluding x1, xt1 input) 0.8v dd 0.2v dd point of measurement 0.8v dd 0.2v dd clock timing 1/f x t xl t xh x1 input v ih3 (min.) v il3 (max.) 1/f xt t xtl t xth xt1 input v ih4 (min.) v il4 (max.) interrupt input timing int t intl t inth key return input timing kr00 to kr03 t kril reset input timing reset t rsl
chapter 18 electrical specifications ( pd179322, 179322a, 179324, 179324a, 179326, and 179327) user?s manual u16995ej2v0ud 203 lcd characteristics (t a = ? 40 to +85 c, v dd = 1.8 to 3.6 v, v lc0 = 1.8 to 5.5 v) parameter symbol conditions min. typ. max. unit vaon0 note 1 = 1 1.8 v lc0 v lcd drive voltage v lcd vaon0 note 1 = 0 2.7 v lc0 v lcd division resistor r lcd 50 100 200 k ? lcd output voltage differential note 2 (common) v odc i o = 5 a 1/3 bias 0 0.2 v lcd output voltage differential note 2 (segment) v ods i o = 1 a 1/3 bias 0 0.2 v notes 1. bit 6 of lcd display mode register 0 (lcdm0). 2. the voltage differential is the di fference between the output voltage and the ideal va lue of the segment and common signal outputs. data memory stop mode low supply voltage data retention characteristics (t a = ? 40 to +85 c, v dd = 1.8 to 3.6 v) parameter symbol conditions min. typ. max. unit data retention supply voltage v dddr 1.8 3.6 v low voltage detection (poc) voltage v poc response time: 2 ms note 1 1.8 1.9 2.0 v supply voltage rise time t pth v dd : 0 v 1.8 v 0.01 100 ms release signal set time t srel stop released by reset 10 s canceled by reset pin or poc note 3 s oscillation stabilization wait time note 2 t wait canceled by interrupt request note 4 s notes 1. the response time is the time unt il the output is inverted following det ection of voltage by poc, or the time until operation stabilizes after the shift from the operation stopped state to the operating state. 2. the oscillation stabilization time is the amount of time the cpu oper ation is stopped in order to avoid unstable operation at the st art of oscillation. program operation does not start until both the oscillation stabilization time and the time until oscillation starts have elapsed. 3. pd78f9328 is fixed to 2 15 /f x . in mask rom versions, 2 15 /f x or 2 17 /f x is selected by a mask option (refer to chapter 16 mask options ). 4. selection of 2 12 /f x , 2 15 /f x , and 2 17 /f x is possible using bits 0 to 2 (o sts0 to osts2) of the oscillation stabilization time select register (osts) (refer to 13.2 register controlling standby function ). remark f x : main system clock oscillation frequency
chapter 18 electrical specifications ( pd179322, 179322a, 179324, 179324a, 179326, and 179327) 204 user?s manual u16995ej2v0ud data retention timing v dd data retention mode stop mode halt mode internal reset operation operating mode t srel t wait stop instruction execution v dddr reset v dd data retention mode stop mode halt mode operating mode t srel t wait stop instruction execution v dddr standby release signal (interrupt request)
user?s manual u16995ej2v0ud 205 chapter 19 electrical specifications ( pd78f9328) absolute maximum ratings (t a = 25 c) parameter symbol conditions ratings unit v dd ? 0.3 to +6.5 v v lc0 ? 0.3 to +6.5 v supply voltage v pp note 1 ? 0.3 to +10.5 v input voltage v i ? 0.3 to v dd + 0.3 note 2 v v o1 p00 to p03, p10, p11, p20 to p22, p40 to p43, p60, p61 ? 0.3 to v dd + 0.3 note 2 v output voltage v o2 com0 to com3, s0 to s16, p80/s22 to p85/s17, s23 ? 0.3 to v lc0 + 0.3 note 2 v pin p60/to40 ? 30 ma per pin (except p60/to40) ? 10 ma output current, high i oh total for all pins (except p60/to40) ? 30 ma per pin 30 ma output current, low i ol total for all pins 80 ma during normal operation ? 40 to +85 c operating ambient temperature t a during flash memory programming 10 to 40 c storage temperature t stg flash memory version ? 40 to +125 c notes 1. make sure that the following conditions of the v pp voltage application timing are satisfied when the flash memory is written. ? when supply voltage rises v pp must exceed v dd 10 s or more after v dd has reached the lower-limit value (1.8 v) of the operating voltage range (a in the figure below). ? when supply voltage falls v dd must be lowered 10 s or more after v pp falls below the lower-limit va lue (1.8 v) of the range of v dd (b in the figure below). 1.8 v v dd 0 v 0 v v pp 1.8 v a b 2. 6.5 v or less caution product quality may suffer if the absolute maximum rating is exceeded even momentarily for any parameter. that is, the absolute maximum rati ngs are rated values at which the product is on the verge of suffering physical damage, and therefore the product must be used under conditions that ensure that the abso lute maximum ratings are not exceeded. remark unless specified otherwise, the characteristics of alternate-functi on pins are the same as those of port pins.
chapter 19 electrical specifications ( pd78f9328) 206 user?s manual u16995ej2v0ud main system clock oscillator characteristics (t a = ? 40 to +85c, v dd = 1.8 to 5.5 v) resonator recommended circuit parameter conditions min. typ. max. unit oscillation frequency (f x ) note 1 1.0 5.0 mhz ceramic resonator x1 x2 c1 c2 oscillation stabilization time note 2 after v dd has reached the oscillation voltage range min. 4 ms oscillation frequency note 1 1.0 5.0 mhz 4.5 v dd 5.5 v 10 ms crystal resonator x1 x2 c1 c2 oscillation stabilization time note 2 1.8 v dd 5.5 v 30 ms x1 input frequency (f x ) note 1 1.0 5.0 mhz external clock x1 x2 x1 input high-/low- level width (t xh , t xl ) 85 500 ns notes 1. indicates only oscillator c haracteristics. refer to ac characteristics for instruction execution time. 2. time required to stabilize oscillation after reset or stop mode release. use t he resonator to stabilize oscillation within the oscillation wait time. cautions 1. when using the ma in system clock oscillator, wire as fo llows in the area enclosed by the broken lines in the above fi gures to avoid an adverse eff ect from wiring capacitance. ? keep the wiring length as short as possible. ? do not cross the wiring with other signal lines. ? do not route the wiring near a signal line th rough which a high fluctuating current flows. ? always make the ground point of the osc illator capacitor the same potential as v ss . ? do not ground the capacitor to a ground patte rn through which a high current flows. ? do not fetch signals from the oscillator. 2. when the main system clock is stopped a nd the device is operating on the subsystem clock, wait until the oscillation stabilization time has been secured by the program before switching back to the main system clock.
chapter 19 electrical specifications ( pd78f9328) user?s manual u16995ej2v0ud 207 recommended oscillation circuit constants ceramic oscillator (t a = ? 40 to +85 c) (flash memory version) recommended circuit constant (pf) oscillation voltage range (v dd ) manufacturer part number frequency (mhz) c1 c2 min. max. remark csbla1m00j58-b0 note 1.0 100 100 2.1 5.5 rd = 3.3 k ? cstcc2m00g56-r0 2.0 cstcr4m00g53-r0 cstls4m00g53-b0 4.0 cstcr4m19g53-r0 cstls4m19g53-b0 4.194 cstcr4m91g53-r0 cstls4m91g53-b0 4.915 cstcr5m00g53-r0 murata mfg. (standard product) cstls5m00g53-b0 5.0 ? ? 1.8 5.5 with internal capacitor fcr4.0mc5 4.0 tdk fcr5.0mc5 5.0 ? ? 2.2 5.5 with internal capacitor pbrc4.00hr 4.0 pbrc4.19hr 4.19 pbrc4.91hr 4.91 kyocera pbrc5.00hr 5.0 ? ? 1.8 5.5 with internal capacitor note when using the csbla1m00j58-b0 of murata mfg. as the ceramic oscilla tor, a limiting resistor (rd = 3.3 k ? ) is necessary (refer to the figure below). the lim iting resistor is not nec essary when other recommended oscillators are used. x2 x1 c2 c1 csbla1m00j58-b0 rd caution the oscillator cons tant is a reference value based on eval uation under a specific environment by the resonator manufacturer. if optimization of oscillator characteristics is necessary in the actual app lication, apply to the resonator manufacturer for evaluati on on the implementation circuit. the oscillation voltage and osc illation frequency indicate only osc illator characteristics. use the pd78f9328 so that the inte rnal operating conditions are within the specifications of the dc and ac characteristics.
chapter 19 electrical specifications ( pd78f9328) 208 user?s manual u16995ej2v0ud subsystem clock oscillator characteristics (t a = ? 40 to +85c, v dd = 1.8 to 5.5 v) resonator recommended circuit parameter conditions min. typ. max. unit oscillation frequency (f xt ) note 1 32 32.768 35 khz 4.5 v dd 5.5 v 1.2 2 s crystal resonator oscillation stabilization time note 2 1.8 v dd 5.5 v 10 s xt1 input frequency (f xt ) note 1 32 35 khz external clock xt1 xt2 xt1 input high-/low- level width (t xth , t xtl ) 14.3 15.6 s notes 1. indicates only oscillator char acteristics. refer to ac characteristics for instruction execution time. 2. the time required for oscillation to stabilize after v dd reaches the min. oscilla tion voltage range. use a resonator to stabilize oscillation during the oscillation wait time. cautions 1. when using the s ubsystem clock oscillator, wire as follo ws in the area enclosed by the broken lines in the above fi gures to avoid an adverse eff ect from wiring capacitance. ? keep the wiring length as short as possible. ? do not cross the wiring with the other signal lines. ? do not route the wiring near a signal line th rough which a high fluctuating current flows. ? always make the ground point of the osc illator capacitor the same potential as v ss . ? do not ground the capacitor to a ground patte rn through which a high current flows. ? do not fetch signals from the oscillator. 2. the subsystem clock osc illator is designed as a low-amplit ude circuit for reducing current consumption, and is more pr one to malfunction due to noise than the main system clock oscillator. particular care is therefore re quired with the wiring method when the subsystem clock is used. remark for the resonator selection and oscillator constant, users are required to eit her evaluate the oscillation themselves or apply to the resonat or manufacturer for evaluation. xt2 xt1 c4 c3 r
chapter 19 electrical specifications ( pd78f9328) user?s manual u16995ej2v0ud 209 dc characteristics (t a = ? 40 to +85c, v dd = 1.8 to 5.5 v) (1/2) parameter symbol conditions min. typ. max. unit per pin 10 ma output current, low i ol total for all pins 80 ma per pin (except p60/to40) ? 1 ma p60/to40 v dd = 3.0 v, v oh = 2.0 v ? 7 ? 15 ? 24 ma output current, high i oh total for all pins (except p60/to40) ? 15 ma 2.7 v dd 5.5 v 0.7v dd v dd v v ih1 p00 to p03, p10, p11, p60, p80 to p85 1.8 v dd 5.5 v 0.9v dd v dd v 2.7 v dd 5.5 v 0.8v dd v dd v v ih2 reset, p20 to p22, p40 to p43, p61 1.8 v dd 5.5 v 0.9v dd v dd v v ih3 x1, x2 v dd ? 0.1 v dd v input voltage, high v ih4 xt1, xt2 v dd ? 0.1 v dd v 2.7 v dd 5.5 v 0 0.3v dd v v il1 p00 to p03, p10, p11, p60, p80 to p85 1.8 v dd 5.5 v 0 0.1v dd v 2.7 v dd 5.5 v 0 0.2v dd v v il2 reset, p20 to p22, p40 to p43, p61 1.8 v dd 5.5 v 0 0.1v dd v v il3 x1, x2 0 0.1 v input voltage, low v il4 xt1, xt2 0 0.1 v v oh11 1.8 v dd 5.5 v, i oh = ? 100 a v dd ? 0.5 v v oh12 p00 to p03, p10, p11, p20 to p22, p40 to p43, p61 1.8 v dd 5.5 v, i oh = ? 500 a v dd ? 0.7 v v oh21 1.8 v dd 5.5 v, i oh = ? 400 a v dd ? 0.5 v v oh22 p60/to40 1.8 v dd 5.5 v, i oh = ? 2 ma v dd ? 0.7 v v oh31 1.8 v dd 5.5 v, i oh = ? 100 a v lc0 ? 0.5 v output voltage, high v oh32 p80/s22 to p85/s17 1.8 v dd 5.5 v, i oh = ? 500 a v lc0 ? 0.7 v v ol11 1.8 v dd 5.5 v, i ol = 400 a 0.5 v v ol12 p00 to p03, p10, p11, p20 to p22, p40 to p43, p60, p61 1.8 v dd 5.5 v, i ol = 2 ma 0.7 v v ol21 1.8 v lc0 5.5 v, i ol = 400 a 0.5 v output voltage, low v ol22 p80/s22 to p85/s17 1.8 v lc0 5.5 v, i ol = 2 ma 0.7 v remark unless specified otherwise, the characteristics of alternate-functi on pins are the same as those of port pins.
chapter 19 electrical specifications ( pd78f9328) 210 user?s manual u16995ej2v0ud dc characteristics (t a = ?40 to +85c, v dd = 1.8 to 5.5 v) (2/2) parameter symbol conditions min. typ. max. unit i lih1 p00 to p03, p10, p11, p20 to p22, p40 to p43, p60, p61, reset, p80 to p85 3 a input leakage current, high i lih2 v in = v dd x1, x2, xt1, xt2 20 a i lil1 p00 to p03, p10, p11, p20 to p22, p40 to p43, p60, p61, reset, p80 to p85 ? 3 a input leakage current, low i lil2 v in = 0 v x1, x2, xt1, xt2 ? 20 a software pull-up resistors r 1 v in = 0 v p00 to p03, p10, p11, p20 to p22, p40 to p43 50 100 200 k ? v dd = 5.5 v note 2 5.0 15.0 ma i dd1 5.0 mhz crystal oscillation operating mode v dd = 3.3 v note 3 2.0 5.0 ma v dd = 5.5 v 1.2 3.6 ma i dd2 5.0 mhz crystal oscillation halt mode v dd = 3.3 v 0.5 1.5 ma v dd = 5.5 v 25 70 a i dd3 32.768 khz crystal oscillation halt mode note 4 v dd = 3.3 v 10 35 a v dd = 5.5 v 2 20 a supply current note 1 i dd4 32.768 khz crystal oscillation stopped stop mode v dd = 3.3 v 1 10 a notes 1. current flowing through ports (including current flowing through on-chip pull-up resistors and from v lc0 to v ss ) is not included. 2. high-speed mode operation (when the processor clo ck control register (pcc) is set to 00h). 3. low-speed mode operation (when pcc is set to 02h) 4. when the main system cl ock operation is stopped. remark unless specified otherwise, the characteristics of alternate-functi on pins are the same as those of port pins.
chapter 19 electrical specifications ( pd78f9328) user?s manual u16995ej2v0ud 211 ac characteristics (1) basic operation (t a = ? 40 to +85c, v dd = 1.8 to 5.5 v) parameter symbol conditions min. typ. max. unit 2.7 v dd 5.5 v 0.4 8.0 s cycle time (min. instruction execution time) t cy 1.8 v dd 5.5 v 1.6 8.0 s interrupt input high-/low-level width t inth , t intl int 10 s key return pin low-level width t kril kr00 to kr03 10 s reset low-level width t rsl 10 s t cy vs. v dd (main system clock) supply voltage v dd (v) 123456 0.1 0.4 0.5 1.0 2.0 10 20 60 cycle time t cy [ s] guaranteed operation range
chapter 19 electrical specifications ( pd78f9328) 212 user?s manual u16995ej2v0ud (2) serial interface 10 (t a = ? 40 to +85 c, v dd = 1.8 to 5.5 v) (a) 3-wire serial i/o mode (internal clock output) parameter symbol conditions min. typ. max. unit v dd = 2.7 to 5.5 v 800 ns sck10 cycle time t kcy1 v dd = 1.8 to 5.5 v 3200 ns v dd = 2.7 to 5.5 v t kcy1 /2-50 ns sck10 high/low-level width t kh1 , t kl1 v dd = 1.8 to 5.5 v t kcy1 /2-150 ns v dd = 2.7 to 5.5 v 150 ns si10 setup time (to sck10 ) t sik1 v dd = 1.8 to 5.5 v 500 ns v dd = 2.7 to 5.5 v 400 ns si10 hold time (from sck10 ) t ksi1 v dd = 1.8 to 5.5 v 800 ns v dd = 2.7 to 5.5 v 0 250 ns delay time from sck10 to so10 output t kso1 r = 1 k ? , c = 100 pf note v dd = 1.8 to 5.5 v 250 1000 ns note r and c are the load resistance and load capacitance of the so10 output line. (a) 3-wire serial i/o mode (external clock input) parameter symbol conditions min. typ. max. unit v dd = 2.7 to 5.5 v 800 ns sck10 cycle time t kcy2 v dd = 1.8 to 5.5 v 3200 ns v dd = 2.7 to 5.5 v 400 ns sck10 high/low-level width t kh2 , t kl2 v dd = 1.8 to 5.5 v 1600 ns v dd = 2.7 to 5.5 v 100 ns si10 setup time (to sck10 ) t sik2 v dd = 1.8 to 5.5 v 150 ns v dd = 2.7 to 5.5 v 400 ns si10 hold time (from sck10 ) t ksi2 v dd = 1.8 to 5.5 v 600 ns v dd = 2.7 to 5.5 v 0 300 ns delay time from sck10 to so10 output t kso2 r = 1 k ? , c = 100 pf note v dd = 1.8 to 5.5 v 250 1000 ns note r and c are the load resistance and load capacitance of the so10 output line.
chapter 19 electrical specifications ( pd78f9328) user?s manual u16995ej2v0ud 213 ac timing measurement points (excluding x1, xt1 input) 0.8v dd 0.2v dd point of measurement 0.8v dd 0.2v dd clock timing 1/f x t xl t xh x1 input v ih3 (min.) v il3 (max.) 1/f xt t xtl t xth xt1 input v ih4 (min.) v il4 (max.) interrupt input timing int t intl t inth key return input timing kr00 to kr03 t kril reset input timing reset t rsl
chapter 19 electrical specifications ( pd78f9328) 214 user?s manual u16995ej2v0ud serial transfer timing 3-wire serial i/o mode: t kcyn t kln t khn sck10 t sikn t ksin t kson si10 so10 input data output data remark n = 1, 2
chapter 19 electrical specifications ( pd78f9328) user?s manual u16995ej2v0ud 215 lcd characteristics (t a = ? 40 to +85 c, v dd = 1.8 to 5.5 v, v lc0 = 1.8 to 5.5 v) parameter symbol conditions min. typ. max. unit vaon0 note 1 = 1 1.8 v lc0 v lcd drive voltage v lcd vaon0 note 1 = 0 2.7 v lc0 v lcd division resistor r lcd 50 100 200 k ? lcd output voltage differential note 2 (common) v odc i o = 5 a 1/3 bias 0 0.2 v lcd output voltage differential note 2 (segment) v ods i o = 1 a 1/3 bias 0 0.2 v notes 1. bit 6 of lcd display mode register 0 (lcdm0). 2. the voltage differential is the di fference between the output voltage and the ideal va lue of the segment and common signal outputs. data memory stop mode low supply voltage data retention characteristics (t a = ? 40 to +85 c, v dd = 1.8 to 5.5 v) parameter symbol conditions min. typ. max. unit data retention supply voltage v dddr 1.8 5.5 v low voltage detection (poc) voltage v poc response time: 2 ms note 1 1.8 1.9 2.0 v supply voltage rise time t pth v dd : 0 v 1.8 v 0.01 100 ms release signal set time t srel stop released by reset 10 s canceled by reset pin or poc 2 15 /f x s oscillation stabilization wait time note 2 t wait canceled by interrupt request note 3 s notes 1. the response time is the time unt il the output is inverted following det ection of voltage by poc, or the time until operation stabilizes after the shift from the operation stopped state to the operating state. 2. the oscillation stabilization time is the amount of time the cpu oper ation is stopped in order to avoid unstable operation at the st art of oscillation. program operation does not start until both the oscillation stabilization time and the time until oscillation starts have elapsed. 3. selection of 2 12 /f x , 2 15 /f x , and 2 17 /f x is possible using bits 0 to 2 (o sts0 to osts2) of the oscillation stabilization time select register (osts) (refer to 13.2 register controlling standby function ). remark f x : main system clock oscillation frequency
chapter 19 electrical specifications ( pd78f9328) 216 user?s manual u16995ej2v0ud data retention timing v dd data retention mode stop mode halt mode internal reset operation operating mode t srel t wait stop instruction execution v dddr reset v dd data retention mode stop mode halt mode operating mode t srel t wait stop instruction execution v dddr standby release signal (interrupt request) writing and erasing characteristics (t a = 10 to 40 c, v dd = 1.8 to 5.5 v) parameter symbol conditions min. typ. max. unit v dd = 2.7 to 5.5 v 1.0 5 mhz write operation frequency f x v dd = 1.8 to 5.5 v 1.0 1.25 mhz write current (v dd pin) note i ddw when v pp supply voltage = v pp1 (at 5.0 mhz operation) 7 ma write current (v pp pin) note i ppw when v pp supply voltage = v pp1 13 ma erase current (v dd pin) note i dde when v pp supply voltage = v pp1 (at 5.0 mhz operation) 7 ma erase current (v pp pin) note i ppe when v pp supply voltage = v pp1 100 ma unit erase time t er 0.5 1 1 s total erase time t era 20 s number of overwrites eras e and write is considered as 1 cycle 20 times v pp0 normal operation 0 0.2v dd v v pp supply voltage v pp1 flash memory programming 9.7 10.0 10.3 v note excludes current flowing through ports (including on-chip pull-up resistors)
user?s manual u16995ej2v0ud 217 chapter 20 package drawing m 39 40 26 52 1 14 13 27 s n s j detail of lead end r k m i s l t p q g f h 52-pin plastic lqfp (10x10) item millimeters a b d g 12.0 0.2 10.0 0.2 0.13 1.1 i 12.0 0.2 j c 10.0 0.2 h 0.32 0.06 0.65 (t.p.) 1.0 0.2 k l 0.5 f 1.1 n p q 0.10 1.4 0.1 0.05 t 0.25 s 1.5 0.1 u 0.6 0.15 s52gb-65-8et-2 m 0.17 + 0.03 ? 0.05 r3 + 4 ? 3 a b cd u
218 user?s manual u16995ej2v0ud chapter 21 recommended soldering conditions the pd179322, 179322a, 179324, 179324a, 179326, 179327, and 78f9328 should be soldered and mounted under the following recommended conditions. for soldering methods and conditions other than those recommended below, please contact an nec electronics sales representative. for technical information, see the following website. semiconductor device mount manual (http ://www.necel.com/pkg/en/mount/index.html) table 21-1. surface mounting ty pe soldering conditions (1/2) (1) pd179322gb- -8et, 179322agb- -8et soldering method soldering conditions recommended condition symbol infrared reflow package peak temperature: 235 c, time: 30 seconds max. (at 210 c or higher), count: twice or less ir35-00-2 vps package peak temperature: 215 c, time: 40 seconds max. (at 200 c or higher), count: twice or less vp15-00-2 wave soldering solder bath temperature: 260 c max., time: 10 seconds max., count: once, preheating temperature: 120 c max. (package surface temperature) ws60-00-1 partial heating pin temperature: 350 c max. time: 3 seconds max. (per pin row) ? (2) pd179324gb- -8et, 179324agb- -8et, 179326gb- -8et, 179327gb- -8et soldering method soldering conditions recommended condition symbol infrared reflow package peak temperature: 235 c, time: 30 seconds max. (at 210 c or higher), count: twice or less, exposure limit: 3 days note (after that, prebake at 125 c for 10 hours) ir35-103-2 vps package peak temperature: 215 c, time: 40 seconds max. (at 200 c or higher), count: twice or less, exposure limit: 3 days note (after that, prebake at 125 c for 10 hours) vp15-103-2 wave soldering solder bath temperature: 260 c max., time: 10 seconds max., count: once, preheating temperature: 120 c max. (package surface temperature), exposure limit: 3 days note (after that, prebake at 125 c for 10 hours) ws60-103-1 partial heating pin temperature: 350 c max. time: 3 seconds max. (per pin row) ? note after opening the dry pack, store it at 25 c or less and 65% rh or less for the allowable storage period. caution do not use different soldering met hods together (except for partial heating).
chapter 21 recommended soldering conditions user?s manual u16995ej2v0ud 219 table 21-1. surface mounting ty pe soldering conditions (2/2) (3) pd78f9328gb-8et soldering method soldering conditions recommended condition symbol infrared reflow package peak temperature: 235 c, time: 30 seconds max. (at 210 c or higher), count: twice or less, exposure limit: 7 days note (after that, prebake at 125 c for 10 hours) ir35-107-2 vps package peak temperature: 215 c, time: 40 seconds max. (at 200 c or higher), count: twice or less, exposure limit: 7 days note (after that, prebake at 125 c for 10 hours) vp15-107-2 wave soldering solder bath temperature: 260 c max., time: 10 seconds max., count: once, preheating temperature: 120 c max. (package surface temperature), exposure limit: 7 days note (after that, prebake at 125 c for 10 hours) ws60-107-1 partial heating pin temperature: 350 c max. time: 3 seconds max. (per pin row) ? (4) pd179322gb-8et-a, 179322agb-8et-a, 179324gb-8e t-a, 179324agb-8et-a, 179326gb-8et-a, 179327gb-8et-a, 78f9328gb-8et-a soldering method soldering conditions recommended condition symbol infrared reflow package peak temperature: 260 c, time: 60 seconds max. (at 220 c or higher), count: three times or less, exposure limit: 7 days note (after that, prebake at 125 c for 20 to 72 hours) ir60-207-3 wave soldering for details, contact an nec electronics sales representative. ? partial heating pin temperature: 350 c max., time: 3 seconds max. (per pin row) ? note after opening the dry pack, store it at 25 c or less and 65% rh or less for the allowable storage period. caution do not use different soldering met hods together (except for partial heating). remark products that have the part numbers suffi xed by "-a" are lead-free products.
220 user?s manual u16995ej2v0ud appendix a development tools the following development tools are avail able for development of systems using the pd179327 subseries. figure a-1 shows development tools. ? support of pc98-nx series unless specified otherwise, the products supported by ibm pc/at? co mpatibles can be used in the pc98-nx series. when using the pc98-nx series, refer to the explanation of ibm pc/at compatibles. ? windows? unless specified otherwise, "windows" i ndicates the following operating systems. ? windows 98 ? windows 2000 ? windows nt? ver.4.0 ? windows xp
appendix a development tools user?s manual u16995ej2v0ud 221 figure a-1. development tools language processing software assembler package c compiler package device file c library source file note 1 software for debugging integrated debugger system simulator host machine (pc or ews) interface adapter in-circuit emulator emulation board emulation probe conversion socket or conversion adapter target system flash programmer flash memory writing adapter flash memory power supply unit software package control software project manager (windows version only) note 2 software package flash memory writing tools notes 1. the c library source file is not included in the software package. 2. the project manager is included in the assemble r package. the project manager is used only for windows.
appendix a development tools 222 user?s manual u16995ej2v0ud a.1 software package various software tools for 78k/0s series development are integrated into one package. the following tools are included. ra78k0s, cc78k0s, id78k0s-ns, sm78k0s, various device files sp78k0s software package part number: s sp78k0s remark in the part number differs depending on the operating system to be used. s sp78k0s host machine os supply medium ab17 japanese windows bb17 pc-9800 series, ibm pc/at compatibles english windows cd-rom a.2 language processing software program that converts program written in mnemonic into obj ect codes that can be executed by microcontroller. in addition, automatic functions to generate sym bol tables and optimize branch instructions are also provided. used in combination with a device file (df179327) (sold separately). the assembler package is a dos-based app lication but may be used in the windows environment by using the proj ect manager of windows (included in the assembler package). ra78k0s assembler package part number: s ra78k0s program that converts program written in c language into objec t codes that can be executed by microcontroller. used in combination with an assembler package (ra78k0s) and device file (df179327) (both sold separately). the c compiler package is a dos-based app lication but may be used in the windows environment by using the proj ect manager of windows (included in the assembler package). cc78k0s c compiler package part number: s cc78k0s file containing the informati on specific to the device. used in combination with the ra78k0s, cc78k0s, and sm78k0s (sold separately). df179327 note1 device file part number: s df179327 source file of functions for generating obj ect library included in c compiler package. necessary for changing object library incl uded in c compiler package according to customer?s specificati ons. since this is a source f ile, its working environment does not depend on any particular operating system. cc78k0s-l note2 c library source file part number: s cc78k0s-l notes 1. df179327 is a common file t hat can be used with the ra78k 0s, cc78k0s, id78k0s-ns, and sm78k0s. 2. cc78k0s-l is not included in the software package (sp78k0s).
appendix a development tools user?s manual u16995ej2v0ud 223 remark in the part number differs depending on the hos t machine and operating system to be used. s ra78k0s s cc78k0s host machine os supply medium ab13 japanese windows bb13 english windows 3.5? 2hd fd ab17 japanese windows bb17 pc-9800 series, ibm pc/at compatibles english windows 3p17 hp9000 series 700? hp-ux? (rel.10.10) 3k17 sparcstation? sunos? (rel.4.1.4), solaris? (rel.2.5.1) cd-rom s df179327 s cc78k0s-l host machine os supply medium ab13 japanese windows bb13 pc-9800 series, ibm pc/at compatibles english windows 3.5? 2hd fd 3p16 hp9000 series 700 hp-ux (rel.10.10) dat 3k13 3.5? 2hd fd 3k15 sparcstation sunos (rel.4.1.4), solaris (rel.2.5.1) 1/4? cgmt a.3 control software project manager control software designed so that t he user program can be e fficiently developed in the windows environment. a series of jobs for us er program development including starting the editor, building, and starting the debugger, can be executed on the project manager. the project manager is included in the assemb ler package (ra78k0s). it cannot be used in an environment other than windows. a.4 flash memory writing tools flashpro iv (part no. fl-pr4, pg-fp4) flash programmer dedicated flash programmer for microcont rollers incorporating flash memory fa-52gb-8et flash memory writing adapter adapter for writing to flash memory and connected to flashpro iii or flashpro iv. fa-52gb-8et: for 52-pin pl astic lqfp (gb-8et type) remark the fl-pr4, and fa-52gb-8et are products made by na ito densei machida mfg. co., ltd. (tel +81- 45-475-4191).
appendix a development tools 224 user?s manual u16995ej2v0ud a.5 debugging tools (hardware) ie-78k0s-ns in-circuit emulator in-circuit emulator for debugging hardware and software of application system using 78k/0s series. supports integrated debugger (id78k0s-n s). used in combination with ac adapter, emulation probe, and interface adapter for connecting the host machine. ie-78k0s-ns-a in-circuit emulator a coverage function has been added to the ie- 78k0s-ns function and the debug function has been further enhanced, enhancing the tracer and timer functions. ie-70000-mc-ps-b ac adapter adapter for supplying power from ac 100 to 240 v outlet. ie-70000-98-if-c interface adapter adapter necessary when using pc-9800 series pc (except notebook type) as host machine (c bus supported) ie-70000-cd-if-a pc card interface pc card and interface cable necessary when using notebook pc as host machine (pcmcia socket supported) ie-70000-pc-if-c interface adapter interface adapter necessary when using ibm pc /at compatible as host machine (isa bus supported) ie-70000-pci-if-a interface adapter adapter necessary when using personal comput er incorporating pci bus as host machine ie-789468-ns-em1 emulation board board for emulating peripheral hardw are specific to devic e. used in combination with in-circuit emulator. np-h52gb-tq emulation probe probe for connecting in-circuit emulator and target system. used in combination with tgb-052sbp. tgb-052sbp conversion adapter conversion adapter to connect np -h52gb-tq and target system board on which 52-pin plastic lqfp (gb-8et type) can be mounted remarks 1. the np-h52gb-tq is a product made by naito densei machida mfg. co., ltd. (tel +81-45-475- 4191). 2. the tgb-052sbp is a product made by tokyo eletech corporation. for further information, c ontact: daimaru kogyo, ltd. tokyo electronics department (tel +81-3-3820-7112) osaka electronics department (tel +81-6-6244-6672)
appendix a development tools user?s manual u16995ej2v0ud 225 a.6 debugging tools (software) a debugger supporting in-circuit emulators fo r the 78k/0s series: ie-78k0s-ns and ie- 78k0s-ns-a. the id78k0s-ns is windows-based software. this program enhances the debugging functions for c language. therefore, it can display the trace results corresponding to the source program by using the window integration function that links the source program, disasse mbled display, and memory display with the trace results. use this program in combination with a device file (df179327) (sold separately). id78k0s-ns integrated debugger part number: s id78k0s-ns a system simulator for the 78k/0s series. the sm78k0s is windows-based software. c-source-level or assembler level debugging is possible while simulating the operation of the target system on the host machine. using the sm78k0s enables logical and performance verification of an application independently of the hardware development. this enhances development efficiency and improves software quality. use this program in combination with a device file (df179327) (sold separately). sm78k0s system simulator part number: s sm78k0s file containing information specific to the device. use this file in combination with the ra 78k0s, cc78k0s, id78k0s-ns, and sm78k0s (sold separately). df179327 note device file part number: s df179327 note df179327 is a common file that can be used with the ra78k0s, cc 78k0s, id78k0s-ns, and sm78k0s. remark in the part number differs depending on the operat ing system to be used and the supply medium. s id78k0s-ns s sm78k0s host machine os supply medium ab13 japanese windows bb13 english windows 3.5? 2hd fd ab17 japanese windows bb17 pc-9800 series, ibm pc/at compatibles english windows cd-rom
appendix a development tools 226 user?s manual u16995ej2v0ud a.7 cautions when designing target system the following shows the conditions when connecting the em ulation probe to the conv ersion adapter. design the system considering shapes and other c onditions of the components to be mount ed on the target system and be sure to follow the configuration below. figure a-2. condition diagram of connection to target system cn2 cn1 in-circuit emulator ie-78k0s-ns or ie-78k0s-ns-a emulation board ie-789468-ns-em1 connect to cn1 if pd179327 subseries is used. emulation probe np-h52gb-tq when cn1 is connected: 370 mm target system conversion adapter: tgb-052sbp conversion adapter: tgb-052sbp emulation probe np-h52gb-tq emulation board ie-789468-ns-em1 10 mm 43 mm 11 mm 45 mm 53 mm no.1 pin 45 mm 23 mm 14.45 mm 14.45 mm target system
user?s manual u16995ej2v0ud 227 appendix b register index b.1 register index (alphabetic order of register name) [c] carrier generator output cont rol register 40 (t ca40) ........................................................................... .................. 93 [e] 8-bit compare regi ster 30 (cr30) ............................................................................................... ............................ 88 8-bit compare regi ster 40 (cr40) ............................................................................................... ............................ 88 8-bit h width compare register 40 (crh 40)...................................................................................... ...................... 88 8-bit timer count er 30 (t m30) .................................................................................................. ............................... 89 8-bit timer count er 40 (t m40) .................................................................................................. ............................... 89 8-bit timer mode contro l register 30 (tmc 30)................................................................................... ...................... 91 8-bit timer mode contro l register 40 (tmc 40)................................................................................... ...................... 92 external interrupt mode register 0 (intm0) ..................................................................................... ..................... 156 [ i ] interrupt mask flag register 0 (mk0) ........................................................................................... .......................... 155 interrupt request flag register 0 (if0)........................................................................................ ............................ 154 [k] key return mode r egister 00 (krm00)............................................................................................ ...................... 157 [l] lcd clock control r egister 0 (lcdc0) ........................................................................................... ....................... 136 lcd display mode r egister 0 (lcdm 0)............................................................................................ ..................... 134 [o] oscillation stabilization time selection regi ster (osts) ....................................................................... ................. 165 [p] port 0 (p0).................................................................................................................... .......................................... 59 port 1 (p1).................................................................................................................... .......................................... 60 port 2 (p2).................................................................................................................... .......................................... 61 port 4 (p4).................................................................................................................... .......................................... 64 port 6 (p6).................................................................................................................... .......................................... 65 port 8 (p8).................................................................................................................... .......................................... 67 port function regi ster 8 (pf8) ................................................................................................. ........................ 70, 137 port mode regist er 0 (p m0) ..................................................................................................... ............................... 68 port mode regist er 1 (p m1) ..................................................................................................... ............................... 68 port mode regist er 2 (p m2) ..................................................................................................... ....................... 68, 128 port mode regist er 4 (p m4) ..................................................................................................... ............................... 68 port mode regist er 6 (p m6) ..................................................................................................... ......................... 68, 94 port mode regist er 8 (p m8) ..................................................................................................... ............................... 68
appendix b register index 228 user?s manual u16995ej2v0ud power-on-clear regi ster 1 (p ocf1) .............................................................................................. ........................150 processor clock cont rol regist er (pcc)......................................................................................... ..........................75 pull-up resistor option register 0 (pu0)....................................................................................... ............................69 pull-up resistor option register b2 (pub2)..................................................................................... .........................70 [s] serial operation mode r egister 10 (csim 10) ..................................................................................... ...................127 subclock control register (css)................................................................................................ ..............................76 suboscillation mode r egister (sckm)............................................................................................ .........................76 [t] transmit/receive shift register 10 (sio 10) ..................................................................................... .......................125 [w] watchdog timer clock select ion register (tcl2) ................................................................................. ..................120 watchdog timer mode r egister (wdtm) ............................................................................................ ...................121 watch timer mode contro l register (wtm)........................................................................................ ....................115
appendix b register index user?s manual u16995ej2v0ud 229 b.2 register index (alphabeti c order of register symbol) [c] cr30: 8-bit compar e regist er 30................................................................................................ ....................... 88 cr40: 8-bit compar e regist er 40................................................................................................ ....................... 88 crh40: 8-bit h width co mpare regi ster 40....................................................................................... ................... 88 csim10: serial operati on mode regi ster 10...................................................................................... .................. 127 css: subclock c ontrol r egister ................................................................................................. ...................... 76 [ i ] if0: interrupt reques t flag regi ster 0 ......................................................................................... .................. 154 intm0: external interr upt mode regi ster 0 ...................................................................................... ................. 156 [k] krm00: key return mode regist er 00 ............................................................................................. ................... 157 [l] lcdc0: lcd clock cont rol regist er 0 ............................................................................................ .................... 136 lcdm0: lcd display mode regist er 0 ............................................................................................. .................. 134 [m] mk0: interrupt mask flag regist er 0............................................................................................ ................... 155 [o] osts: oscillation stabilization time selecti on regi ster........................................................................ ............. 165 [p] p0: port 0..................................................................................................................... ................................ 59 p1: port 1..................................................................................................................... ................................ 60 p2: port 2..................................................................................................................... ................................ 61 p4: port 4..................................................................................................................... ................................ 64 p6: port 6..................................................................................................................... ................................ 65 p8: port 8..................................................................................................................... ................................ 67 pcc: processor clo ck control register.......................................................................................... ................... 75 pf8: port functi on regist er 8 .................................................................................................. ................ 70, 137 pm0: port mode register 0 ...................................................................................................... ........................ 68 pm1: port mode register 1 ...................................................................................................... ........................ 68 pm2: port mode register 2 ...................................................................................................... ................ 68, 128 pm4: port mode register 4 ...................................................................................................... ........................ 68 pm6: port mode register 6 ...................................................................................................... .................. 68, 94 pm8: port mode register 8 ...................................................................................................... ........................ 68 pocf1: power-on-cl ear regist er 1 ............................................................................................... ..................... 150 pu0: pull-up resistor option regi ster 0 ........................................................................................ .................... 69 pub2: pull-up resistor option regi ster b2...................................................................................... .................... 70 [s] sckm: suboscillati on mode r egister............................................................................................. ..................... 76 sio10: transmit/receive shift regi ster 10...................................................................................... ................... 125
appendix b register index 230 user?s manual u16995ej2v0ud [t] tca40: carrier generator out put control r egister 40............................................................................ ...............93 tcl2: watchdog timer clo ck selection regist er .................................................................................. ............120 tm30: 8-bit time r counter 30................................................................................................... ..........................89 tm40: 8-bit time r counter 40................................................................................................... ..........................89 tmc30: 8-bit timer mode control regi ster 30 .................................................................................... ...................91 tmc40: 8-bit timer mode control regi ster 40 .................................................................................... ...................92 [w] wdtm: watchdog time r mode r egister............................................................................................. ................121 wtm: watch timer m ode control regist er......................................................................................... ..............115
user?s manual u16995ej2v0ud 231 appendix c revision history c.1 major revisions in this edition page description throughout addition of pd179322a and 179324a p. 231 addition of c.2 revision history of preceding editions c.2 revision history of preceding editions here is the revision history of the preceding editi ons. chapter indicates the chapter of each edition. page description p. 15 addition of lead-free products to 1.3 ordering information p. 218 addition of lead-free products to chapter 21 recommended soldering conditions
nec electronics corporation 1753, shimonumabe, nakahara-ku, kawasaki, kanagawa 211-8668, japan tel: 044-435-5111 http://www.necel.com/ [america] nec electronics america, inc. 2880 scott blvd. santa clara, ca 95050-2554, u.s.a. tel: 408-588-6000 800-366-9782 http://www.am.necel.com/ [asia & oceania] nec electronics (china) co., ltd 7th floor, quantum plaza, no. 27 zhichunlu haidian district, beijing 100083, p.r.china tel: 010-8235-1155 http://www.cn.necel.com/ nec electronics shanghai ltd. room 2509-2510, bank of china tower, 200 yincheng road central, pudong new area, shanghai p.r. china p.c:200120 tel: 021-5888-5400 http://www.cn.necel.com/ nec electronics hong kong ltd. 12/f., cityplaza 4, 12 taikoo wan road, hong kong tel: 2886-9318 http://www.hk.necel.com/ seoul branch 11f., samik lavied?or bldg., 720-2, yeoksam-dong, kangnam-ku, seoul, 135-080, korea tel: 02-558-3737 nec electronics taiwan ltd. 7f, no. 363 fu shing north road taipei, taiwan, r. o. c. tel: 02-2719-2377 nec electronics singapore pte. ltd. 238a thomson road, #12-08 novena square, singapore 307684 tel: 6253-8311 http://www.sg.necel.com/ for further information, please contact: g05.12a [europe] nec electronics (europe) gmbh arcadiastrasse 10 40472 dsseldorf, germany tel: 0211-65030 http://www.eu.necel.com/ hanover office podbielski strasse 166 b 30177 hanover tel: 0 511 33 40 2-0 munich office werner-eckert-strasse 9 81829 mnchen tel: 0 89 92 10 03-0 stuttgart office industriestrasse 3 70565 stuttgart tel: 0 711 99 01 0-0 united kingdom branch cygnus house, sunrise parkway linford wood, milton keynes mk14 6np, u.k. tel: 01908-691-133 succursale fran?aise 9, rue paul dautier, b.p. 52180 78142 velizy-villacoublay cdex france tel: 01-3067-5800 sucursal en espa?a juan esplandiu, 15 28007 madrid, spain tel: 091-504-2787 tyskland filial t?by centrum entrance s (7th floor) 18322 t?by, sweden tel: 08 638 72 00 filiale italiana via fabio filzi, 25/a 20124 milano, italy tel: 02-667541 branch the netherlands limburglaan 5 5616 hr eindhoven the netherlands tel: 040 265 40 10

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